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Beginner
107 Views

3.3V supply for 3.0V LVCMOS

Hi,

I'm using a Cyclone 5 with a SDRAM. 
I have a 3.3V supply on all my VVCIO's but for signal integrity we would use the 
on chip series termination of 50Ohm.
This is not possible for 3.3V LVCMOS but it is for 3.0V LVCMOS.
What are the consequences if doing so? Turning my supply to 3.0V is not an option.

With kind regards,

Wouter Platteau

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4 Replies
Employee
88 Views

Hi Wouter Platteau

For those IO standard that doesn't support On Chip Termination (OCT), and yes for 3.3V LVCMOS, we should implement external termination.

Thanks

Eng Wei

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Beginner
80 Views

I do understand that external termination is the proper solution in this case.
But could you tell me the consequences of selecting 3.0 LVCMOS as the IO standard 
but supplying 3V3 on the VCCIO pins?

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Beginner
69 Views

Assigning a bank a voltage in Quartus defines the bank as that voltage. In this case, the bank would become a 3.0v bank. Checking the Recommended Operating Conditions in the Datasheet, VCCIO for a 3.0v bank is allowed to be a max of 3.15v, so even at the nominal 3.3v value of a 3.3v VCCIO, it would be out of spec. That means that some percentage of the devices would not function correctly.

Interestingly, VCCIO for a 3.3v bank is allowed to be a minimum of 3.135v, which overlaps with the 3.0v range. So it would be possible to tune the 3.3v supply down to 3.14v, and use it with both 3.0v and 3.3v banks.

While this is technically feasible, it would require power supplies with very tight tolerances, which are much more expensive than adding external termination.

The only clean solution that I see is to add another VRM to the board, and that is also probably the cheapest solution.

Happy Friday!!!

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Employee
42 Views

Hi Wouter Platteau

You have to refer to Table 15 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_51002.pdf for the Vccio spec per I/O standard. This is the guaranteed functionality covered by Engineering Team. 

 

Thanks.

Eng Wei

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