5CEBA7F27C8N FPGA GPIO Pins Setup and Hold time

[ShivaKi]

Hello,

For FPGA 5CEBA7F27C8N, a parallel interface to be implemented using GPIO pins. 

While performing write operation into FPGA from external processor,

1. what will be the setup and holdtime of FPGA IO pins?

Please provide timings/any reference documentation

[AqidAyman_Intel]

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[AqidAyman_Intel]

Hi,

I am not an expert in the timing area, but I know that you can use a logic setting inside Quartus to see if the setup and hold time was violated. Refer to link below:

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#logicops/logicops/def_setup_hold_time_violation_detection.htm

[AqidAyman_Intel]

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