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5CEBA7F27C8N FPGA IO Pin Status After Power ON Reset

ShivaKi
Beginner
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Hello,

 

For FPGA 5CEBA7F27C8N, 

 

1. What will be the status of IO Pins after Power ON Reset, when IO pins are configured as 

    a. Input

    b.Output

    c. Input/Output

 

2. What will be the status of IO Pins after Functional Reset(reset implemented through coding), when IO pins are configured as 

    a. Input

    b.Output

    c. Input/Output

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AqidAyman_Intel
Employee
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We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum cases, along with others, did not get through as intended. As a result, we have a backlog of cases that we are currently working through one by one.

Please be assured that we are doing everything we can to resolve this issue as quickly as possible. However, this process will take some time, and we kindly ask for your patience and understanding during this period. The cases will be attended by AE shortly.

We appreciate your patience and understanding, and we are committed to providing you with the best support possible.

Thank you for your understanding.


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AqidAyman_Intel
Employee
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Hello,


  1. After Power On Reset (POR), all the I/Os pins are tied to an internal weak pull-up before entering the user mode.
  2. After functional reset, the I/O pins will behave following the logic you assigned in your code. It is dependent on the design itself.


Regards,

Aqid


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AqidAyman_Intel
Employee
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I hope the previous response was sufficient to help you proceed. As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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