7 Segment display

Altera_Forum · ‎08-23-2017

Is there a way to choose a certain seven segment display and disable the other 7 on the DE2-115 board. For example is it possible to put a statement like SSEG <= "11111110" which would disable all of the seven segment displays except for the very first one. Thanks in advance for the help

Altera_Forum · ‎08-23-2017

Yes, there is (and, as with many of these things there are many ways to do so...). Two for starters:

You could 'AND' each 7-segment output with a bit from your SSEG value (note this doesn't consider whether the display bits are on when the output is driven high or low).

You could test each SSEG value, with an 'if' statement, to determine how to drive the display.

Cheers

Alex

Altera_Forum · ‎08-23-2017

The code is as follows.

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity MUX_0thruF is

Port ( SW : in STD_LOGIC_VECTOR (4 downto 0);

SEL : in STD_LOGIC;

a_to_g : out STD_LOGIC_VECTOR (6 downto 0);

an : out STD_LOGIC_VECTOR (7 downto 0);

dp : out STD_LOGIC;

LD0 : out STD_LOGIC);

end MUX_0thruF;

architecture Behavioral of MUX_0thruF is

begin

LD0 <= SW(4);

dp <= not SW(4);

process(SW)

begin

case SW is

when "00000"=> a_to_g <="1000000";

when "00001"=> a_to_g <="1111001";

when "00010"=> a_to_g <="0100100";

when "00011"=> a_to_g <="0110000";

when "00100"=> a_to_g <="0011001";

when "00101"=> a_to_g <="0010010";

when "00110"=> a_to_g <="0000010";

when "00111"=> a_to_g <="1111000";

when "01000"=> a_to_g <="0000000";

when "01001"=> a_to_g <="0011000";

when "01010"=> a_to_g <="0001000";

when "01011"=> a_to_g <="0000011";

when "01100"=> a_to_g <="1000110";

when "01101"=> a_to_g <="0100001";

when "01110"=> a_to_g <="0000110";

when "01111"=> a_to_g <="0001110";

when "1----"=> a_to_g <="0000000";

when others => a_to_g <="1111111";

end case;

end process;

process(SEL)

begin

case SEL is

when '0' => an <= "11111110";

when '1' => an <= "01111111";

when others => an <= "11111111";

end case;

end process;

end Behavioral;

The problem I am having is the last part

process(SEL)

begin

case SEL is

when '0' => an <= "11111110";

when '1' => an <= "01111111";

when others => an <= "11111111";

end case;

end process;

I want to be able to use a switch to turn on one seven segment display then switch to another if I choose to. However that would entail shutting all the seven segment displays except for one. Then turning that one off and turning the other one on. This would also mean that instead of declaring the actual parts of the seven segment display, I would have to declare a whole display to be able to turn in on or off. I do not see a pin assignment for the whole display. I was able to do that for the switches which was declared as a vector and for the "a_to_g". I was able to use the pin assighments and declare what each one is. However I do not see where in the pin declaration, how to declare a whole segment display. The only information I am seeing is HEX0[0], HEX0[1], HEX0[2], .... So I originally thought I can declare a whole dislay as HEX0 but the system is telling me that is not a valid pin assignment. Can someone help me with this please. Also, I do not see a pin assignment for the decimal point or dp. Thank you.

Altera_Forum · ‎08-24-2017

To answer your last question first, the 'dp' may not be connected up on the DE2-115 board - I don't remember off hand but that's certainly the case for some Dev boards. This may explain why it's missing from the pinout.

As for the code - use 'a_to_g' as an intermediate signal. Create a new output that feeds the display. Assuming 'SEL' is one bit of your previously mentioned 'SSEG' signal, use it in a different way, with a conditional statement to determine what to do:

if SEL = '1' then
  a_to_g_to_display <= a_to_g;
else
  a_to_g_to_display <= "1111111";   -- your code reminds me these display segments are ON when pin is driven LOW
end if;

Place the above code in a combinatorial process triggered by 'SEL' & 'a_to_g'.

I can't comment on the 'SW', 'an' or 'LD0' signals - it's not clear what they're for...

Cheers,

Alex

Altera_Forum · ‎08-24-2017

Thank you for your help. I will try that.