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Valued Contributor III
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8 MHz clock from 100 MHz

I am generating 8 MHz clock by scaling down the 100 MHz clock. The design I have implemented simulates well but when loaded on MAX-10 and observed using Signal Tap II logic analyzer the clock signal behaves completely different. Its period and duty cycle varies across the waveform.<br><img src="https://alteraforum.com/forum/attachment.php?attachmentid=15822&amp;stc=1" attachmentid="15822" alt="Simulation" id="vbattach_15822" class="previewthumb"><br><img src="https://alteraforum.com/forum/attachment.php?attachmentid=15823&amp;stc=1" attachmentid="15823" alt="As observed on Logic Analyzer" id="vbattach_15823" class="previewthumb"> Any guess why its behaves like this? 

 

The design is based on a counter in verilog: 

 

always @ (clk) begin if (clk_counter < 5'b01011) begin clk_counter <= clk_counter + 5'b00001; end else if (clk_counter == 5'b01011) begin SCLK <= 1'b1; clk_counter <= clk_counter + 5'b00001; end else if ((clk_counter > 5'b01011) && (clk_counter < 5'b11001)) begin clk_counter <= clk_counter + 5'b00001; end else if (clk_counter >= 5'b11001) begin SCLK <= 1'b0; clk_counter <= 5'b00000; end end
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Valued Contributor III
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You may be undersampling in Signal Tap depending on what you are using as the sampling clock in the tool. Why don't you just use a PLL? 

 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/max-10/ug_m10_clkpll.p...
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Valued Contributor III
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Did you attach the right code? It looks like SCLK is driven 0 when clk_counter is 0 and SCLK is driven to 1 when clk_counter is 13, then the clk_counter gets set back to 0 it reaches 25. So 26 100Mhz clock ticks doesn't result in a 125ns SCLK period. 

 

By the way a clock divider is easier to understand if you just use a free running modulo counter and drive your output clock based on that counter being above or below a threshold. So if I was attempting to generate a clock close to 8MHz from a 100MHz source (you can't achieve exactly 8MHz by the way) I would have a 100MHz counter that cycles after it hits 12 then for count values below 7 drive sclk to 0, and above 7 drive sclk to 1 (assign sclk = (clk_counter < 5'h7)? 1'b0 : 1'b1). To minimize jitter I would also pipeline that sclk before driving any logic or pins with it. 

 

Keep in mind that logic generated clocks will jitter more than a PLL output will. PLLs will be able to achieve the 8MHz frequency unlike a clock divider as well.
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Valued Contributor III
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@sstrel 

 

I am using a 50MHz clock for sampling in SignalTap II. Not much familiar with the PLL and also because of licensing issue of IP cores thought to skip it, but looks like that is the most feasible option. Thanks 

 

@BadOmen 

Yes you are right I mistakenly shared a different version of the code where the triggering limits for SCLK are different. Correct version is shared below with changes emboldened. 

always @ (clk) begin if (clk_counter < 5'b01011) begin clk_counter <= clk_counter + 5'b00001; end else if (clk_counter == 5'b01011) begin SCLK <= 1'b1; clk_counter <= clk_counter + 5'b00001; end else if ((clk_counter > 5'b01011) && (clk_counter < 5'b11001)) begin clk_counter <= clk_counter + 5'b00001; end else if (clk_counter == 5'b11001) begin SCLK <= 1'b0; clk_counter <= 5'b00000; end end  

 

 

Thank you for the reply. Actually this always block is triggered on both the edges of 100MHz clock. Since the 100MHz clock was needed to be scaled down by a factor of 12.5 and triggering on single edge would not have resulted in exactly 8MHz output clock. So what I did is that I compromised on 50% duty cycle of the clock by triggering the counter on both the edges and counted 12 edges for SCLK 's low logic and 13 edges for SCLK 's high logic to count 25 half-periods (or 12.5 full-periods) of 100MHz clock. Had the scaling factor been a positive integer I would definitely used a modulo counter. 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=15843  

 

I will try to make use of PLL but would still appreciate if someone can help me in diagnosing the reason of this unusual behavior of the 8MHz clock in Logic Analyzer.
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Valued Contributor III
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PLLs do not require additional licensing. 

 

Where is the 50 MHz clock you are using for sampling coming from?
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Beginner
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Actually I am using the DE-10 Lite board and the 50 MHz clock is coming from on-board clock.

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Employee
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Like others have said the PLL isn't a licensed IP, all FPGAs have them and it's what I would think of as a basic feature (like on-chip RAM blocks for example). I would use the PLL wizard flow and not attempt to instantiate it manually in your RTL, it'll have a lot of parameters so using the wizard will save you a lot of typing and reading up on the IP. When you use the wizard you tell it your input clock is 50MHz and then you state you want an output clock of 8MHz and it will create an 8MHz clock (or as close as possible frequency). One thing to keep in mind is that it takes a PLL a while to "lock" so you should hold the logic it's connected to in reset until the locked signal from the PLL goes high. The locked signal is an optional signal so while you are in the wizard you'll see a checkbox to include it. When the PLL comes out of reset and is not locked yet you will see the output clock jitter which can cause stability issues in your own hardware so holding your hardware in reset waiting for the PLL to lock is a safe way to avoid this issue.

 

Once you are done with the wizard it'll generate some files for you that set the PLL up. You can use one of the wrapper files in your own RTL to instantiate it. If you have to adjust the PLL to change the frequency or maybe have it drive more clocks then you can reopen the wizard on the same PLL you previously generated.

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