8b10b clock recovery?

[Altera_Forum]

Would it be possible to use an Altera FPGA (Arria II GX or Cyclone IV GX) to snoop on a 2.5 Gbps PCI Express link (via the PIPE interface), recover the clock and send out the recovered clock to one of the differential outputs? One of the differential output signals could then be used to trigger a scope for eye-diagram testing. The scope would then connect both channels to the diff signals (possibly using the math function to recreate the differential signal in the scope). 

 For this to work, the recovered output clock signal must be in phase with the input differential signal.  Thanks.

[Altera_Forum]

What kind of data are you hoping to collect about the signal? The jitter is going to be quite high using the method you're describing. 

 Also you can only get the recovered parallel domain clock (125MHz or maybe 250MHz). But you don't need the serial clock to trigger a scope, the parallel clock is fine.  Jitter is the biggest problem. If it were me, I'd look for an external reclocker or deserializer IC (with a passthrough) and get the clock that way.  Jake

[Altera_Forum]

Yes, i suspected that jitter would be the main problem. 

 My initial though was to clock the scope with one of the signals in the differential pair. This, of course, means that jitter will not be measurable since the scope will always trigger on the rising (or falling) edge of the signal, effectively not displaying the jitter. Since i want to primarily use this setup to measure the signal quality after having passed the PCI Express signals through a passive extender board i am really only interested in the rise/fall times as well as the amplitude of the signals before and after the extender board.  My plan is to create my own PCI Express Load Board similar to the one once sold by intel. These boards simply connect the signals in the differential pair coming from the motherboard to a SMA connector that terminates with 50 ohm in the scope. This would enable me to use a low-cost 6 GHz bandwidth sampling/digitizing scope to monitor the signal degradation with and without the PCI express extender board. I would assume the jitter to be the same before and after the extender board since jitter would largely be a property of the transmitter, not the transmission line?  Also, would the recovered clock have less jitter than the signal it was embedded in? If not, i might as well just trigger on the measured signal itself instead of recovering the clock.  Could you recommend an external clock recovery circuit?

[Altera_Forum]

Any changes in the impedance between the transmitter and receiver can certainly contribute to jitter. This includes all transmission lines and their interconnects. Also, the effect of the transmission line's loss is not necessarily considered jitter but it can look like jitter on the scope as the eye closes in from the left and right (rising and falling edges). 

 You might have a look at mindspeed: http://www.mindspeed.com/web/product/category.html?id=2022&trail=2001 Have a look at their retimers and CDR products. Maybe one will work for you.  Also, what is the end destination of the PCI Express link? Tapping in the middle of that line to get a look at the signal is most certainly not going to look pleasant.  Jake

[Altera_Forum]

Thanks for the Mindspeed link. It looks like none of their circuits actually output a clock but are used for re-sending high-speed serial data. 

 When thinking a bit more about the problem; is it even neccesary to recover the clock? I am only interested in the behavior of the rising and falling edges as well as the corresponding ampliture. Doesn't this mean that i can trigger on any rising/falling edges and that the underlying clock therefore is irrelevant?  The end destination of the PCI Express link is the oscilloscope itself. The differential signal pair will go from the motherboard, through the extender board, through the load board (that has the SMA connectors) and into the oscilloscope where the signals are terminated in 50 ohm. In other words, the 'load board' is really just a PCIe board that connects all downstream differential signals to SMA connectors.  Thanks.

[Altera_Forum]

It's not obvious to me, that a recovered CDR clock brings an advantage for your measurements. But may be I didn't understand the intention exactly. The practical problems of tapping a PCIe link without disturbing it should be well considered. A differential active probe would be the best solution. A matched resistive "power divider" involves a 6 dB attenuation. 

 Most PCIe system are using a spread spectrum reference clock, which adds additional jitter to any PLL or recovery circuit, that locks to the clock. All PCIe Tx signals are however locked to the 125 MHz reference clock, so you may want to try, if this clock isn't suitable for triggering the measurements. It's jitter should be "two PLL steps" lower than your intended CDR circuit.

[Altera_Forum]

--- Quote Start ---  The practical problems of tapping a PCIe link without disturbing it should be well considered. A differential active probe would be the best solution. A matched resistive "power divider" involves a 6 dB attenuation.  --- Quote End ---    In the proposed measurement setup, the PCIe link will not be tapped but rather terminated (in the scope). In the most simple setup case, the 'SMA board' is plugged directly into a motherboard PCIe connector:  Transmitter => PCIe Slot => 'SMA board' => Oscilloscope  Note that the only purpose of the 'SMA board' is to connect the two signals in the PCIe signal pair to the single-ended scope channels. The intent is to avoid using a probe at all and instead use the 'infinite bandwidth' coaxial cable and the termination in the scope, essentially extending the transmission line all the way into the scope's 50 ohm termination.    --- Quote Start ---   Most PCIe system are using a spread spectrum reference clock, which adds additional jitter to any PLL or recovery circuit, that locks to the clock. All PCIe Tx signals are however locked to the 125 MHz reference clock, so you may want to try, if this clock isn't suitable for triggering the measurements. It's jitter should be "two PLL steps" lower than your intended CDR circuit.  --- Quote End ---    Assuming that the jitter can be ignored (the extender board will only have some three inches long traces), is there any reason why the above setup could not be useful for a 'rough' measurement of the PCIe eye diagram? I am essentially interested in knowing whether the extender board substantially changes the signal quality.  My plan is to first plug the 'SMA board' into the motherboard PCIe slot and capture the signal forms. Then install the extender board and plug in the 'SMA board' on top and do the same measurement. If the two measurements are roughly equivalent, then the extender board should be safe to use.  Also, given that the scope is triggered on the data, SSC should not affect the measurements.  Thanks.

[Altera_Forum]

Well now I understand a bit more. So you don't really need to "tap" the signal at all. The scope is your endpoint. There is no reason why you can't just use the data signal as your scope trigger. So you can go ahead and use the negated side of the pair as a trigger. 

 I did a fairly extensive investigation on scope triggering methods for FPGA transceiver outputs. Basically your best case jitter is if you reclock the data and use the recovered clock to trigger the scope viewing the reclocked data. Second best case jitter is to recover the clock and use it to trigger the scope viewing non-reclocked data. I tested about 8 different methods. Using the complementary data signal to trigger the scope came in 6th.   However, the test case was for pathological SDI data and your 8b/10b will perform better. Also, all you care about is rise/fall times and amplitude. You'll be fine.  Jake

[Altera_Forum]

Thank you for clarifying, I didn't get the simple setup. It should work this way.  

 Regarding the purpose of your measurement, a transmission line actually is not contributing jitter to the signal directly. It's main influence is frequency dependant signal attenuation, it's also causing reflections at the connectors, possibly generating cross-talk (e.g. between RX and TX pairs). In so far it can affect the eye-diagram quality. Crosstalk can convert to signal edge jitter, signal attenuation can increase the jitter of the succeeding receiver. (The latter can't be seen directly).

[Altera_Forum]

Thanks both of you for confirming my measurement method.

[Altera_Forum]

--- Quote Start ---  Basically your best case jitter is if you reclock the data and use the recovered clock to trigger the scope viewing the reclocked data.   --- Quote End ---    This is not a good option for me because i would no longer look at the actual data on the 2nd downstream PCIe connector.    --- Quote Start ---  Second best case jitter is to recover the clock and use it to trigger the scope viewing non-reclocked data.   --- Quote End ---    How did you recover the clock? I have found no circuit that actually outputs the clock from a 2.5 gbps 8b/10b diff signal. If the solution is fairly simple i could build this circuitry into the 'SMA board' and get better overall result.     --- Quote Start ---   I tested about 8 different methods. Using the complementary data signal to trigger the scope came in 6th.   However, the test case was for pathological SDI data and your 8b/10b will perform better. Also, all you care about is rise/fall times and amplitude. You'll be fine.  Jake  --- Quote End ---    This may be good enough if i can't figure out how to do the clock recovery.  Thanks.

[Altera_Forum]

If it were me, I'd just use the complementary data signal to trigger the scope. 

 Jake

[Altera_Forum]

Alright, this is what i'll do. Thanks.

[Altera_Forum]

--- Quote Start ---  My initial though was to clock the scope with one of the signals in the differential pair. This, of course, means that jitter will not be measurable since the scope will always trigger on the rising (or falling) edge of the signal, effectively not displaying the jitter.   --- Quote End ---    I need to correct myself. Jitter is defined as variations in the high or low bit times and due to this, the jitter will be visible as variations in the signal transitions in the right part of the eye diagram. Therefore, it should be fine to trigger the scope on one of the differential signals. It will not be accordingly to the PCIe spec's compliance rules but it will be useful as a comparison tool to find out whether signal degradation occurs in my setup.

[Altera_Forum]

PCIe spec is a good point. In my understanding, it uses the reference clock as trigger in performance meaurements, as I already suggested.

[Altera_Forum]

Just to tie up all loose ends: 

   --- Quote Start ---  Second best case jitter is to recover the clock and use it to trigger the scope viewing non-reclocked data.   --- Quote End ---    How did you recover the clock? I have found no circuit that actually outputs the clock from a 2.5 gbps 8b/10b diff signal. If the solution is fairly simple i could build this circuitry into the 'SMA board' and get better overall result.   Thanks.

[Altera_Forum]

As I mentioned before. I was working with 3G SDI data not 2.5G 8b10b. There are a plethora of products that provide CDR for SDI. 

 Jake

[Altera_Forum]

--- Quote Start ---  I have found no circuit that actually outputs the clock from a 2.5 gbps 8b/10b diff signal.  --- Quote End ---   The Mindspeed CDR devices mentioned by jakobjones e.g. do.

[Altera_Forum]

I could not see any recovered clock being output from the mindspeed devices. I however did not see any datasheet but rather block diagrams. 

 If i'm not mistaken there is a 100 MHz reference clock that must be sent along with the differential signals. Since this should be phase aligned with the diff signals, or at the very least have low jitter in relation to the data, would it be possible to use the reference clock to trigger the scope?  Also, must i feed the differential reference clock into the Cyclone IV for it to be able to consume the differential high-speed PCI express data? I searched the Cyclone IV handbook but could not find must information (it is late, though so i might have missed it).  Thanks.

[Altera_Forum]

I saw a block diagram of a Mindspeed 4 channel CDR, that has Data inputs and Clock + Data outputs. Clock means recovered clock in my understanding. 

 As I previously mentioned, the PCIe Refclk can be used as a trigger for jitter measurements, because all Tx signals are phase locked to it. See also PCie 2.0 Base Spec chapter 4.3.2. jitter budgeting and measurement for a discussion of the PCIe jitter model.  If you use REFCLK as a trigger, you see the transmitter fully contributing to measured jitter. But I don't think that this is a problem in comparative measurements.

[Altera_Forum]

--- Quote Start ---  the PCIe Refclk can be used as a trigger for jitter measurements, because all Tx signals are phase locked to it.  --- Quote End ---    Thanks. I came to the same conclusion and this is what i'll do.