A PLL problem.

EEren · ‎12-14-2023

I created a new project for MAX10 10M50SAE144I7G and copied a PLL and ADC modules in it.

component pll is
port
(
	 inclk0 : in std_logic := '0';
	 c0	 : out std_logic;
	 c1	 : out std_logic;
	 c2	 : out std_logic;
	 c3	 : out std_logic  
);
end component;

component adc_qsys is
port 
(
	adc_1_command_valid          : in  std_logic                     := '0';             --  adc_1_command.valid
	adc_1_command_channel        : in  std_logic_vector(4 downto 0)  := (others => '0'); -- .channel
	adc_1_command_startofpacket  : in  std_logic                     := '0';             -- .startofpacket
	adc_1_command_endofpacket    : in  std_logic                     := '0';             -- .endofpacket
	adc_1_command_ready          : out std_logic;                                        -- .ready
	adc_1_response_valid         : out std_logic;                                        -- adc_1_response.valid
	adc_1_response_channel       : out std_logic_vector(4 downto 0);                     -- .channel
	adc_1_response_data          : out std_logic_vector(11 downto 0);                    -- .data
	adc_1_response_startofpacket : out std_logic;                                        -- .startofpacket
	adc_1_response_endofpacket   : out std_logic;                                        -- .endofpacket
		
	clk_clk                      : in  std_logic                     := '0';             --  clk.clk
	reset_reset_n                : in  std_logic                     := '0'              --  reset.reset_n
);
end component;

-----------------------------------------------------------------------------------------------------------------
  
U_SYS_PLL : pll 
port map
(
    inclk0  => OBE_CLK,
	 c0		=> s_pll_clk_120M,
	 c1      => s_pll_clk_100M,
	 c2      => s_pll_clk_30M,
	 c3      => s_pll_clk_10M
);

U_SYS_ADC : adc_qsys 
port map 
(
	clk_clk        => s_pll_clk_10M,
	reset_reset_n  => '1', 
	
	adc_1_command_valid          => adc1_com_valid, 
	adc_1_command_channel        => adc1_com_channel, 
	adc_1_command_startofpacket  => adc1_com_startofpacket,
	adc_1_command_endofpacket    => adc1_com_endofpacket, 
	adc_1_command_ready          => adc1_com_ready,
	adc_1_response_valid         => adc1_resp_valid,
	adc_1_response_channel       => adc1_resp_channel,
	adc_1_response_data          => adc1_resp_data, 
	adc_1_response_startofpacket => adc1_resp_startofpacket,
	adc_1_response_endofpacket   => adc1_resp_endofpacket
);

And it compiles OK.

Then I added a process for all channels scan.

type AdcStateType is (ST_WAIT_FOR_TRIG, ST_SELECT_CHAN, ST_SET_CHAN, 
                      ST_START_CONV, ST_WAIT_FOR_DONE, ST_DATA_READY);
signal Adc1State : AdcStateType := ST_WAIT_FOR_TRIG;


SYS_ADC_SCAN : process(glob_clock)
variable chan : integer range 0 to 9 := 0;
begin

    if rising_edge(glob_clock) then
	 
        case Adc1State is
	 
            when ST_WAIT_FOR_TRIG =>
  
                adc1_ena <= '1';
                chan := 0;
                adc1_com_valid <= '0';
					
                if (adc1_start = '1') then		 
                    Adc1State <= ST_SELECT_CHAN;
                end if;
					
            when ST_SELECT_CHAN =>
                adc1_ena <= '0';
                chan := chan + 1;
                if (chan >  then   
                    Adc1State <= ST_WAIT_FOR_TRIG;
                else
                   case chan is
                       when 1 => adc1_com_channel <= "00000";   
                       when 2 => adc1_com_channel <= "00001";
                       when 3 => adc1_com_channel <= "00010";
                       when 4 => adc1_com_channel <= "00011";
                       when 5 => adc1_com_channel <= "00100";
                       when 6 => adc1_com_channel <= "00101";
                       when 7 => adc1_com_channel <= "00110";
                       when 8 => adc1_com_channel <= "00111";
                       when others => 
                   end case;
                    Adc1State <= ST_START_CONV;
			    end if;	
					
            when ST_START_CONV => 
                adc1_com_valid <= '1';
                Adc1State <= ST_WAIT_FOR_DONE;
			
            when ST_WAIT_FOR_DONE =>
                if (adc1_resp_valid = '1') then
                    Adc1State <= ST_DATA_READY;
                end if;
                --timeout
                adc1_timeout <= adc1_timeout + '1';
                if (adc1_timeout >= X"249F00") then  --20 ms
                     adc1_timeout <= (others => '0');
                     Adc1State <= ST_WAIT_FOR_TRIG;
                  end if;
					
            when ST_DATA_READY => 
                adc1_com_valid <= '0';
                case chan is
                    when 1 => adc1_1_data <= adc1_resp_data;   
                    when 2 => adc1_2_data <= adc1_resp_data;
                    when 3 => adc1_3_data <= adc1_resp_data;
                    when 4 => adc1_4_data <= adc1_resp_data;
                    when 5 => adc1_5_data <= adc1_resp_data;  
                    when 6 => adc1_6_data <= adc1_resp_data;
                    when 7 => adc1_7_data <= adc1_resp_data;
                    when 8 => adc1_8_data <= adc1_resp_data;
                    when others => Adc1State <= ST_WAIT_FOR_TRIG;
                end case;
                Adc1State <= ST_SELECT_CHAN;	
				  
            when others => 
                 Adc1State <= ST_WAIT_FOR_TRIG;	  
				
        end case;				
			
    end if;
end process SYS_ADC_SCAN;

And Fitter generates an error

Info (15535): Implemented PLL "pll:U_SYS_PLL|altpll:altpll_component|pll_altpll:auto_generated|pll1" as MAX 10 PLL type
Info (15535): Implemented PLL "adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll|adc_qsys_ADC1_PLL_altpll_gr22:sd1|pll7" as MAX 10 PLL type
    
    
Error (176394): Can't fit 2 PLLs in the device -- only 1 PLLs are available
    Info (176395): Location PLL_3 cannot be used due to package or device migration constraints
    Info (176395): Location PLL_4 cannot be used due to package or device migration constraints

So I started to comment out the process lines and found out that if I remove the line adc1_com_valid <= '1'; in here

when ST_START_CONV => 
    --adc1_com_valid <= '1';
    Adc1State <= ST_WAIT_FOR_DONE;

It compiles OK. How this signal makes the fitter to generate internal ADC's PLL as a system one?

sstrell · ‎12-14-2023

Where is glob_clock coming from?

EEren · ‎12-16-2023

It's coming from PLL

U_SYS_PLL : pll port map

(inclk0 => OBE_CLK,

c0 => s_pll_clk_120M,

c1 => s_pll_clk_100M,

c2 => s_pll_clk_30M,

c3 => s_pll_clk_10M );

glob_clock <= s_pll_clk_120M;

sstrell · ‎12-16-2023

The PLL output driving the ADC must be c0 of PLL1 or PLL3 of the device. The no fit may be because you are not doing this. Switch the PLL outputs around to drive the ADC with c0 and see if that fixes the problem.

EEren · ‎12-16-2023

Isn't it the same signal? Any way I've chaged it

SYS_ADC_SCAN : process(s_pll_clk_120M) --c0 from PLL
variable chan : integer range 0 to 9 := 0;
begin

    if rising_edge(s_pll_clk_120M) then

----------------------------------------

and the ADC module gets 10 Mhz clock as it should

U_SYS_ADC : adc_qsys 
port map 
(
    clk_clk        => s_pll_clk_10M, --c3 from PLL
    reset_reset_n  => '1',

The problem still remains.

sstrell · ‎12-17-2023

Like I said, it can't come from c3. You have to edit the PLL parameters and have the clock you want to use for the ADC to come from the c0 output of the PLL. So the c0 output should be 10 MHz and move the 120 MHz clock to c3.

EEren · ‎12-17-2023

OK. I see. So I redesigned the PLL in Q-SYS. And now it's

U_SYS_PLL : pll port map
(
inclk0 => OBE_CLK,
c0 => s_pll_clk_10M, 
c1 => s_pll_clk_100M,
c2 => s_pll_clk_30M,
c3 => s_pll_clk_120M 
);

But I get the same error.

sstrell · ‎12-18-2023

So the tool thinks a clock is needed somewhere else and is implementing an additional PLL for some reason. I think you'll have to check the timing analyzer to see all the clocks in your design to try to figure it out. Generate a clocks report to see all the domains. This might help you narrow down what is going on.

EEren · ‎12-19-2023

I see. To what item in the timing analyzer report should I pay attention. Going through the report couldn't find a clue.

I have a project with the same ADC module that compiles nad runs good. I compare two reports

------------------ GOOD PROJECT -----------------------

Source assignments for adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll
Source assignments for adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll|adc_qsys_ADC1_PLL_stdsync_sv6:stdsync2|adc_qsys_ADC1_PLL_dffpipe_l2c:dffpipe3

Port Connectivity Checks: "adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll|adc_qsys_ADC1_PLL_altpll_gr22:sd1"
Port Connectivity Checks: "adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll"

------------------ BAD PROJECT -----------------------

Source assignments for adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll
Source assignments for adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll|adc_qsys_ADC1_PLL_stdsync_sv6:stdsync2|adc_qsys_ADC1_PLL_dffpipe_l2c:dffpipe3

Port Connectivity Checks: "adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll|adc_qsys_ADC1_PLL_altpll_gr22:sd1"
Port Connectivity Checks: "adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll"

The two reports are the same. But the Fitter reports are different. And Fitter processed on earlier stage, before timing analyzer.

------------------ GOOD PROJECT -----------------------

+------------------------------------------------------------------------------------------------------+
; PLL Summary ;
+-------------------------------+----------------------------------------------------------------------+
; Name ; pll:U_SYS_PLL|altpll:altpll_component|pll_altpll:auto_generated|pll1 ;
+-------------------------------+----------------------------------------------------------------------+
; SDC pin name U_SYS_PLL|altpll_component|auto_generated|pll1 ;
; PLL mode Normal ;
; Compensate clock clock0 ;
; Compensated input/output pins -- ;
; Switchover type -- ;
; Input frequency 0 30.0 MHz ;
; Input frequency 1 -- ;
; Nominal PFD frequency 30.0 MHz ;
; Nominal VCO frequency 600.0 MHz ;
; VCO post scale K counter 2 ;
; VCO frequency control Auto ;
; VCO phase shift step 208 ps ;
; VCO multiply -- ;
; VCO divide -- ;
; Freq min lock 15.0 MHz ;
; Freq max lock 32.51 MHz ;
; M VCO Tap 0 ;
; M Initial 1 ;
; M value 20 ;
; N value 1 ;
; Charge pump current setting 1 ;
; Loop filter resistance setting 24 ;
; Loop filter capacitance setting 0 ;
; Bandwidth 450 kHz to 980 kHz ;
; Bandwidth type Medium ;
; Real time reconfigurable Off ;
; Scan chain MIF file -- ;
; Preserve PLL counter order Off ;
; PLL location PLL_1 ;
; Inclk0 signal MBT_CLK ;
; Inclk1 signal -- ;
; Inclk0 signal type Dedicated Pin ;
; Inclk1 signal type -- ;
+-------------------------------+----------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PLL Usage ;
+----------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-------------------------------------------------------+
; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name ;
+----------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-------------------------------------------------------+
; pll:U_SYS_PLL|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] ; clock0 ; 10 ; 3 ; 100.0 MHz ; 0 (0 ps) ; 7.50 (208 ps) ; 50/50 ; C0 ; 6 ; 3/3 Even ; -- ; 1 ; 0 ; U_SYS_PLL|altpll_component|auto_generated|pll1|clk[0] ;
+----------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-------------------------------------------------------+

------------------ BAD PROJECT -----------------------

+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PLL Summary ;
+-------------------------------+----------------------------------------------------------------------+--------------------------------------------------------------------------------------+
; Name ; pll:U_SYS_PLL|altpll:altpll_component|pll_altpll:auto_generated|pll1 ; adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll|adc_qsys_ADC1_PLL_altpll_gr22:sd1|pll7 ;
+-------------------------------+----------------------------------------------------------------------+--------------------------------------------------------------------------------------+
; SDC pin name U_SYS_PLL|altpll_component|auto_generated|pll1 U_SYS_ADC|adc1_pll|sd1|pll7 ;
; PLL mode Normal Normal ;
; Compensate clock clock0 clock0 ;
; Compensated input/output pins -- -- ;
; Switchover type -- -- ;
; Input frequency 0 30.0 MHz 10.0 MHz ;
; Input frequency 1 -- -- ;
; Nominal PFD frequency 30.0 MHz 10.0 MHz ;
; Nominal VCO frequency 600.0 MHz 400.0 MHz ;
; VCO post scale K counter 2 2 ;
; VCO frequency control Auto Auto ;
; VCO phase shift step 208 ps 312 ps ;
; VCO multiply -- -- ;
; VCO divide -- -- ;
; Freq min lock 15.0 MHz 7.5 MHz ;
; Freq max lock 32.51 MHz 16.25 MHz ;
; M VCO Tap 0 0 ;
; M Initial 1 1 ;
; M value 20 40 ;
; N value 1 1 ;
; Charge pump current ; setting 1 setting 1 ;
; Loop filter resistance ; setting 24 setting 20 ;
; Loop filter capacitance ; setting 0 setting 0 ;
; Bandwidth ; 450 kHz to 980 kHz 450 kHz to 590 kHz ;
; Bandwidth type ; Medium Medium ;
; Real time reconfigurable ; Off Off ;
; Scan chain MIF file ; -- -- ;
; Preserve PLL counter order ; Off Off ;
; PLL location ; Unassigned Unassigned ;
; Inclk0 signal OBE_CLK ; pll:U_SYS_PLL|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[3] ;
; Inclk1 signal -- -- ;
; Inclk0 signal type Dedicated Pin Global Clock ;
; Inclk1 signal type -- -- ;
+-------------------------------+----------------------------------------------------------------------+--------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PLL Usage ;
+--------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-------------------------------------------------------+
; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name ;
+--------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-------------------------------------------------------+
; pll:U_SYS_PLL|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] ; clock0 ; 4 ; 1 ; 120.0 MHz ; 0 (0 ps) ; 9.00 (208 ps) ; 50/50 ; C0 ; 5 ; 3/2 Odd ; -- ; 1 ; 0 ; U_SYS_PLL|altpll_component|auto_generated|pll1|clk[0] ;
; pll:U_SYS_PLL|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] ; clock2 ; 1 ; 1 ; 30.0 MHz ; 0 (0 ps) ; 2.25 (208 ps) ; 50/50 ; C1 ; 20 ; 10/10 Even ; -- ; 1 ; 0 ; U_SYS_PLL|altpll_component|auto_generated|pll1|clk[2] ;
; pll:U_SYS_PLL|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[3] ; clock3 ; 1 ; 3 ; 10.0 MHz ; 0 (0 ps) ; 0.75 (208 ps) ; 50/50 ; C2 ; 60 ; 30/30 Even ; -- ; 1 ; 0 ; U_SYS_PLL|altpll_component|auto_generated|pll1|clk[3] ;
; adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll|adc_qsys_ADC1_PLL_altpll_gr22:sd1|wire_pll7_clk[0] ; clock0 ; 1 ; 1 ; 10.0 MHz ; 0 (0 ps) ; 1.13 (312 ps) ; 50/50 ; C0 ; 40 ; 20/20 Even ; -- ; 1 ; 0 ; U_SYS_ADC|adc1_pll|sd1|pll7|clk[0] ;
+--------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-------------------------------------------------------+

In the latter report Fitter detecs two PLL's.

lixy · ‎01-07-2024

Hi EEren,

May I know if this issue has been fixed?

Based on previous information, it looks like we need to check in Quartus RTL or technology map and see where is the other PLL from?

Best Regards,

XY

A PLL problem.

Configuration (FPGA)