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hello expert,
We uses Arria10 PCIe HIP core to build a EP device. In general, the FPGA works fine when plugging inside x86 SERVER PCIE Slot at most cases .
But for a part of x86 servers, we found A10 PCIe HIP “"nreset_status"” signal will be deasserted sometimes and randomly, while at that moment PCIe HIP's " npor & pin_pers " signals keep at High. According to " ug-01145_avmm-1_0.pdf " description, "
apps_rstn, which is derived from npor or pin_perstn. |
"
Thus one word to say , in our exceptional case, eventhough either "npor" or " pin_perstn " keeps to "high", " apps_rstn " still be deasserted to LOW (0). I want to find why it happens ?
Appreciate any helps.
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Hi,
Could you share the signaltap with signals below? What is the speed grade and lane number used?
pll_cal_busy
tx_cal_busy[n-1:0]
rx_cal_busy[n-1:0]
pin_perst
npor
reset_status
pld_clk_inuse
pll_locked
rx_is_lockedtoref[n-1:0]
rx_is_lockedtodata[n-1:0]
rx_std_signaldetect[n-1:0]
ltssmstate[4:0]
lane_act[3:0]
currentspeed[1:0]
rx_ready[n-1:0]
tx_ready[n-1:0]
rx_analogreset[n-1:0]
rx_digitalreset[n-1:0]
tx_analogreset[n-1:0]
tx_digitalreset[n-1:0]
tx_st*
rx_st*
Thanks
Best regards,
KhaiY
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Thanks @KhaiChein_Y_Intel for reply,
We checked PCIe HIP part library code, and found below code. To my understanding, this "output reset_status" signal dedrived from "reset_status_hip" signal, while the "reset_status_hip" comes from :
twentynm_hssi_gen3_x8_pcie_hip { .reset_status (reset_status_hip), } ;
My puzzle is : what does this "hssi_gen3_x8_pcie_hip { .reset_status )" stand for ?
At what condition, this "hssi_gen3_x8_pcie_hip { .reset_status )" would be deasserted ?
ThankS a lot !!
[ ==
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Hi,
Does the transceiver calibration successful? Can you check if the pin_perst of the Hard IP instance connects to the corresponding nPERST pin of the device correctly? Could you share the signal tap result?
These pins have the following locations:
• NPERSTL0: bottom left Hard IP and CvP blocks
• NPERSTL1: top left Hard IP block
• NPERSTR0: bottom right Hard IP block
• NPERSTR1: top right Hard IP block
Thanks
Best regards,
KhaiY
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Hi,
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Best regards,
KhaiY
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I am seeing what sounds like same problem.
I have created post: A10 PCIe Device not seen by Windows - Intel Community
that includes SigTap capture.

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