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Valued Contributor III
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ADC output from LVDS deserializer.

Hi, 

 

I have a an ADC sampling at 40 MHz, and it output LVDS signal, so i have to deserialize it using my DE2-115, but i am having trouble with the deserialized signal (shown in the picture), it should display a pure sine wave. 

I have no idea what are the possible solution. I am using the lvds_rx block provided from megawizard.  

I have not set the .SDC file yet, you think that might solve the problem?  

 

 

Please comment.. 

 

regards, 

Michael
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Valued Contributor III

Re: ADC output from LVDS deserializer.

since the noise you have on your signal is not diffuse I suspect it not analogue but is due to fpga io or timing inside. You can see that most of the error is due to bit 11 ringing and one or so other bits.

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Valued Contributor III

Re: ADC output from LVDS deserializer.

I agree that the problem is probably timing issue. 

So, how should i define the timing constraint in .SDC ?  

and how is it going to help solving the problem? 

 

Michael
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Valued Contributor III

Re: ADC output from LVDS deserializer.

you will need your sdc certainly and a word of caution about the way you sample your signaltap, use the same data clock

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Valued Contributor III

Re: ADC output from LVDS deserializer.

you need to enter your clock and check the tCO of your ADC device and then use set input constraints accordingly for tSU and tH. see examples 

in altera website, timequest design centre
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Valued Contributor III

Re: ADC output from LVDS deserializer.

 

--- Quote Start ---  

you will need your sdc certainly and a word of caution about the way you sample your signaltap, use the same data clock 

--- Quote End ---  

 

 

 

IIUC, by data clock, you mean the frame clock (slow clock) of LVDS ?  

 

 

 

 

--- Quote Start ---  

 

you need to enter your clock and check the tCO of your ADC device and then use set input constraints accordingly for tSU and tH. see examples 

in altera website, timequest design centre  

 

--- Quote End ---  

Thank you very much KAZ! i will try according to your advice.! 

 

Michael
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Valued Contributor III

Re: ADC output from LVDS deserializer.

I am not familiar with your particular setup as ADCs come with various formats. If you mean you deserialise your ADC raw data arriving at 40 M bits per sec then the data clock is that of 40/12 (frame clock if that is what you mean by frame clock). Do not divide the clock through logic as that will cause timing problems. 

 

When you write first sdc you will be possibly swearing at altera but focus on clock entry and set input delay.
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Valued Contributor III

Re: ADC output from LVDS deserializer.

 

--- Quote Start ---  

 

When you write first sdc you will be possibly swearing at altera but focus on clock entry and set input delay. 

--- Quote End ---  

 

 

 

Oh.. yea!... i thought timing constraint stuffs were done automatically, since i inputted the clock speed, input data rate in Megawizard, so i thought Quartus 2 is smart enough to extract required information from these wizard generated files.
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Valued Contributor III

Re: ADC output from LVDS deserializer.

Are sure, that the receiver clock phase has been set correctly according to the ADC timing?

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Valued Contributor III

Re: ADC output from LVDS deserializer.

 

--- Quote Start ---  

Are sure, that the receiver clock phase has been set correctly according to the ADC timing? 

--- Quote End ---  

 

 

 

I am sure i did not do that. 

and How do i do that?? 

 

Attached is the output timing characteristic of my ADC (i want it to run at 40MHz) 

so far, i have this in my .SDC 

 

create_clock -period 4.15 [get_ports HSMC_CLKIN_P2] # this is because the input of LVDS is at 240 MHz, due to (40MHz*12bits/2 = 240MHz)i guess... 

 

derive_pll_clocks 

 

 

derive_clock_uncertainty 

 

set_input_delay -clock HSMC_CLKIN_P2 -max .61 [all_inputs] 

set_input_delay -clock HSMC_CLKIN_P2 -min 0.55 [all_inputs] 

 

 

I am sure these are wrong, cause the shape of sine wave reconstructed is worst.  

 

 

Michael
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Valued Contributor III

Re: ADC output from LVDS deserializer.

Your sdc looks ok to me. Check report if you indeed got that.  

You will also need lvds termination, go to project settings (assignment editor). 

 

If it is DDR, you will need constraints for both edges. 

You can also try rotate the PLL clock if you are using pll if you can't pass timing. 

 

Moreover, it could be timing not at io but at point when you sample the data on to 40MHz. Note 40MHs clock is edge aligned with data and you better do some shift away from edge e.g sample on opposite edge.
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Valued Contributor III

Re: ADC output from LVDS deserializer.

 

--- Quote Start ---  

Your sdc looks ok to me. Check report if you indeed got that.  

 

--- Quote End ---  

 

 

There is too much report data, i don't know where to look. 

Is this the one i should be looking for ? 

 

Info: Worst-case setup slack is 0.202 

Info: Slack End Point TNS Clock  

Info: ========= ============= ===================== 

Info: 0.202 0.000 inst|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[0]  

Info: 3.436 0.000 inst|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[1]  

Info: 47.987 0.000 altera_reserved_tck  

Info: Assembler is generating device programming files 

Info: Worst-case hold slack is 0.160 

Info: Slack End Point TNS Clock  

Info: ========= ============= ===================== 

Info: 0.160 0.000 altera_reserved_tck  

Info: 0.162 0.000 inst|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[1]  

Info: 0.170 0.000 inst|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[0]  

Info: Worst-case recovery slack is 49.169 

Info: Slack End Point TNS Clock  

Info: ========= ============= ===================== 

Info: 49.169 0.000 altera_reserved_tck  

Info: Worst-case removal slack is 0.471 

Info: Slack End Point TNS Clock  

Info: ========= ============= ===================== 

Info: 0.471 0.000 altera_reserved_tck  

Info: Worst-case minimum pulse width slack is 1.251 

Info: Slack End Point TNS Clock  

Info: ========= ============= ===================== 

Info: 1.251 0.000 inst|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[0]  

Info: 1.867 0.000 HSMC_CLKIN_P2  

Info: 12.205 0.000 inst|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[1]  

Info: 49.285 0.000 altera_reserved_tck  

Info: Design is not fully constrained for setup requirements 

Info: Design is not fully constrained for hold requirements 

Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 18 warnings 

Info: Peak virtual memory: 280 megabytes 

Info: Processing ended: Sat Oct 15 19:37:28 2011 

Info: Elapsed time: 00:00:04 

Info: Total CPU time (on all processors): 00:00:03 

Info: Quartus II Assembler was successful. 0 errors, 0 warnings 

Info: Peak virtual memory: 413 megabytes 

Info: Processing ended: Sat Oct 15 19:37:29 2011 

Info: Elapsed time: 00:00:05 

Info: Total CPU time (on all processors): 00:00:05 

Info: Quartus II Full Compilation was successful. 0 errors, 517 warnings 

 

 

 

--- Quote Start ---  

 

If it is DDR, you will need constraints for both edges. 

You can also try rotate the PLL clock if you are using pll if you can't pass timing. 

 

--- Quote End ---  

like this ?. 

create_clock -period 4.15 [get_ports HSMC_CLKIN_P2] 

create_clock -period 4.15 [get_ports HSMC_CLKIN_N2] 

 

set_input_delay -clock HSMC_CLKIN_P2 -max 0.61 [get_ports HSMC_RX_D_P[11]] 

 

set_input_delay -clock HSMC_CLKIN_P2 -min 0.55 [get_ports HSMC_RX_D_P[11]] 

 

set_input_delay -clock HSMC_CLKIN_P2 -max 0.61 [get_ports HSMC_RX_D_N[11]] 

 

set_input_delay -clock HSMC_CLKIN_P2 -min 0.55 [get_ports HSMC_RX_D_N[11]] 

 

 

 

 

 

--- Quote Start ---  

 

Moreover, it could be timing not at io but at point when you sample the data on to 40MHz. Note 40MHs clock is edge aligned with data and you better do some shift away from edge e.g sample on opposite edge. 

--- Quote End ---  

I get what you mean, but how do i do "shifting away from the edge" ? 

 

 

 

Thank you for your advice. 

 

 

Michael
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Valued Contributor III

Re: ADC output from LVDS deserializer.

I should add, the results of reconstructed wave seems to look alot better (attached) after setting .SDC and doing LVDS termination as you suggested, but there are still rooms for improvement.

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Valued Contributor III

Re: ADC output from LVDS deserializer.

The table doesn't directly specify data to frame clock relation. It tells implicitely, that frame clock and data are in phase, which is the case for other LVDS interface ADCs I've been working with (Analog and TI). This means, that the PLL must generate a phase shift of about 90° for the fast clock related to the frame clock to sample the data in the window center. 

 

You can't set this phase shift by timing constraints, it has to be set in the PLL parameters. Personally, I prefer to adjust the phase shift parameter manually by centering it between the margins. (Apparently, you have already found one margin). But if you start with a reasonable value, the design can be expected to operate at moderate speeds. 

 

Cyclone IV also offers an option to tune the phase automatically by utilizing the PLL dynamic phase shift feature. But I think, this is only meaningful for a design operating near the LVDS speed limit, where sampling windows are pretty small. And there's no ready made Altera IP for this purpose. 

 

It would be helpful, if you tell the actual ADC type. 

 

Regards, 

Frank 

 

P.S.: I didn't yet read your latest posts. The last shows that you are moving in the right direction, but the clock phase is still at the sampling window margin. Most likely, it has to be shifted just by 90 degree.
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Valued Contributor III

Re: ADC output from LVDS deserializer.

 

--- Quote Start ---  

The table doesn't directly specify data to frame clock relation.  

--- Quote End ---  

 

yes .. you are right, this is something i've overlooked before i read the timing contraint cook book "Source Synchronous Timing with TimeQuest"written by Ryan Scoville aka rysc in this forum. 

 

 

--- Quote Start ---  

 

You can't set this phase shift by timing constraints, it has to be set in the PLL parameters.  

--- Quote End ---  

are you sure ? are you sure i can't do it like this in the timing constraint? or do you mean the PLL output from ADC ? 

 

create_clock -period 4.15 -name bitclk create_clock -period 4.15 -name extbitclk -waveform {1.038 3.113} derive_pll_clocks derive_clock_uncertainty set relationship 1.038 # these are from datasheet of TI's AFE5808 set adc_tsu 0.55 set adc_th 0.61 set adc_skew_max ; set adc_skew_min ; set board_data2clk_skew_max 0.05 set board_data2clk_skew_min -0.05 set TIADC_in_max ; set TIADC_in_min ; set_input_delay -clock extbitclk -max $TIADC_in_max }] set_input_delay -clock extbitclk -min $TIADC_in_min }] set_input_delay -clock extbitclk -max $TIADC_in_max }] -clock_fall -add_delay set_input_delay -clock extbitclk -min $TIADC_in_min }] -clock_fall -add_delay  

--- Quote Start ---  

Cyclone IV also offers an option to tune the phase automatically by utilizing the PLL dynamic phase shift feature. 

 

--- Quote End ---  

ya.. but it is only available in the CYCLONE 4 GX or Stratix, not CYCLONE 4 E 

 

 

 

--- Quote Start ---  

 

It would be helpful, if you tell the actual ADC type. 

 

--- Quote End ---  

it is TI's AFE 5808 EVM, i just found out this is center aligned data lvds output(the bit clock and lvds data are 90 degree out of phase with each other) 

 

 

 

I found out that, when i use lvds_rx core from megawizard, and set the phase shift to expect to be 90 degree.. everything works fine!! even without the timing constraint file above. 

 

So i was wondering if the .SDC file is actually usefull here, so i made the phase shift to expect back to 0 degree, and with the contraint file.. the reconstructed wave will again appears to have lots of noise... 

 

 

so it seems like the .SDC file does not do anything here.. i am confused, whats wrong with my timing constraint above?  

 

 

 

 

Michael
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Valued Contributor III

Re: ADC output from LVDS deserializer.

 

--- Quote Start ---  

The table doesn't directly specify data to frame clock relation. It tells implicitely, that frame clock and data are in phase, which is the case for other LVDS interface ADCs I've been working with (Analog and TI). This means, that the PLL must generate a phase shift of about 90° for the fast clock related to the frame clock to sample the data in the window center. 

 

--- Quote End ---  

 

 

 

I should add, the ADC i am working with, do comes with a bit clock (fast clock ) which is already 90 degree shifted for me. it is done inside the ADC. 

so i dont really need an extra PLL to phase shift it 90 degree. 

 

 

Michael
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Valued Contributor III

Re: ADC output from LVDS deserializer.

 

--- Quote Start ---  

 

 

I found out that, when i use lvds_rx core from megawizard, and set the phase shift to expect to be 90 degree.. everything works fine!! even without the timing constraint file above. 

 

So i was wondering if the .SDC file is actually usefull here, so i made the phase shift to expect back to 0 degree, and with the contraint file.. the reconstructed wave will again appears to have lots of noise... 

 

 

so it seems like the .SDC file does not do anything here.. i am confused, whats wrong with my timing constraint above?  

 

Michael 

--- Quote End ---  

 

 

Sounds right to me. If you use LVDS_rx and it asks for data/clk relationship then I wonder why need sdc. Looks like timing control has two tier approach. Frankly I never came across any TimeQuest doc on such double tier timing control. 

 

 

Obviously we have at least two areas which are timing critical, bit stream sampling at fpga using fast clock and parallel data sampling using data clock. 

 

When you used lvds_rx I guess you also used its output clock for parallel data out instead of ADC frame clock (which is edge aligned with serial data). That should do the job. In that case I come to believe like you that simply use sdc for other than set input delay. In fact I will try set false path on all data/frame clk inputs and see what happens.  

 

The other issue you haven't cleared is that do you use DDR IF and how to do convert it inside FPGA to SDR single data rate as this affects the clocking scheme you are using.
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Valued Contributor III

Re: ADC output from LVDS deserializer.

 

--- Quote Start ---  

 

The other issue you haven't cleared is that do you use DDR IF and how to do convert it inside FPGA to SDR single data rate as this affects the clocking scheme you are using. 

--- Quote End ---  

 

 

 

I want to use DDR format at the input and SDR at the output. i think it is done automatically by using altlvds_rx from the megawizard. Attached is the table that i extracted from the user guide of altlvds_rx. 

 

[J is the deserialization factor] 

 

 

Michael
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Valued Contributor III

Re: ADC output from LVDS deserializer.

 

--- Quote Start ---  

I should add, the ADC i am working with, do comes with a bit clock (fast clock ) which is already 90 degree shifted for me. it is done inside the ADC. so i dont really need an extra PLL to phase shift it 90 degree. 

--- Quote End ---  

 

 

That's right. I assume, that the bitclock is just O.K. for the said 480 MBPS data rate. Near the Cyclone III speed limits, you may find an option to adjust the receiver phase helpful. This is much easier with a PLL. 

 

 

--- Quote Start ---  

but it is only available in the CYCLONE 4 GX or Stratix, not CYCLONE 4 E 

--- Quote End ---  

 

The said dynamic PLL dynamic phase shift feature is available for all Cyclone III - V FPGAs. It's a functionality you can use in your design, there's no ready-to-use IP block provided by Altera. 

 

 

--- Quote Start ---  

I want to use DDR format at the input and SDR at the output. i think it is done automatically by using altlvds_rx from the megawizard. 

--- Quote End ---  

 

Output from the LVDS_RX block is always SDR parallel data with the rate of the "slow clock" respectively frame clock. 

 

Synchronization of received data to your system clock may be an additional issue. In your initial example, you simply used the LVDS_RX output clock. This is convenient but mostly doesn't fir the design requirements.
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Valued Contributor III

Re: ADC output from LVDS deserializer.

 

--- Quote Start ---  

 

 

The said dynamic PLL dynamic phase shift feature is available for all Cyclone III - V FPGAs. It's a functionality you can use in your design, there's no ready-to-use IP block provided by Altera. 

 

--- Quote End ---  

 

 

really? that would be great!..is it called DPA (dynamic shift alignment) ? how do we activate this function? cause last time i check with altlvds_rx in Megawizard, it was grayed out, and someone in the forum said DPA is not available to Cyclone series. 

 

 

--- Quote Start ---  

 

Synchronization of received data to your system clock may be an additional issue. In your initial example, you simply used the LVDS_RX output clock. This is convenient but mostly doesn't fir the design requirements. 

--- Quote End ---  

would you mind explaining further on this? can i use a DCFIFO to capture the parallel data? would it solve the problem? 

 

 

Michael
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