ADC output from LVDS deserializer.

[Altera_Forum]

Hi, 

 I have a an ADC sampling at 40 MHz, and it output LVDS signal, so i have to deserialize it using my DE2-115, but i am having trouble with the deserialized signal (shown in the picture), it should display a pure sine wave. I have no idea what are the possible solution. I am using the lvds_rx block provided from megawizard.  I have not set the .SDC file yet, you think that might solve the problem?    Please comment..  regards, Michael

[Altera_Forum]

The AdcOut[11] is wrong. I am sure. The AdcOut[9] is wrong, maybe. So check all wire length.

[Altera_Forum]

Sorry, the AdcOut[10] is wrong.

[Altera_Forum]

http://www.alteraforum.com/forum/D:\\adc20output.JPG

[Altera_Forum]

I do not know how to upload picture.

[Altera_Forum]

--- Quote Start ---  is it called DPA (dynamic shift alignment) ? how do we activate this function? cause last time i check with altlvds_rx in Megawizard, it was grayed out, and someone in the forum said DPA is not available to Cyclone series.  --- Quote End ---    DPA is a feature of hardware LVDS_RX blocks in Stratix and Arria FPGA family and allows an automatic sampling phase correction of individual bits under some prerequisites. It's in fact not available with Cyclone FPGAs.  Dynamic phase shift is a basic feature of the PLL blocks since Cyclone III. It can be used to achieve a DPA-like functionality with the LVDS PLL, but not for individual bits. Unlike with hardware DPA, that can be simply enabled in the MegaWizard, you have to design the phase shift state machine and signal edge detector yourself.  @eRen: Your point isn't clear. There's no doubt about wrong bits in the ADC data. The original poster also reported, that he was able to fix the problem. Length mismatch can't explain the failure of individual bits in this case, because it's a serial LVDS data transmission over a single differential pair, so all bits undergo the same delay.

[Altera_Forum]

What FvW said is reasonable. Maybe add a NOT gate in outclock will resovle the problem. 

 What kind of the ADC? AFE5851?AFE5801?   The mismatch may between the clock signal and data signal, or the lvds p and lvds n.

[Altera_Forum]

From the AdcOut picture, the spurs cover all over sina signal. The big spurs are caused by the Msb bit, the small spurs caused by the Lsb bit. So, I guess the possiblity of mismatch is very high.

[Altera_Forum]

If the mismatch is between the clock and data signals, you can try the method: 

  HSMC_RX_D_P -> PLL( the output frequency is same as the input, adjusting the phase ) -> LVDS12401 -> DCFIFO

[Altera_Forum]

--- Quote Start ---   Dynamic phase shift is a basic feature of the PLL blocks since Cyclone III. It can be used to achieve a DPA-like functionality with the LVDS PLL, but not for individual bits. Unlike with hardware DPA, that can be simply enabled in the MegaWizard, you have to design the phase shift state machine and signal edge detector yourself.   --- Quote End ---     well.. its good to know it can be done.. but i have absolutely no idea how to do that.   Michael

[Altera_Forum]

--- Quote Start ---  If the mismatch is between the clock and data signals, you can try the method:    HSMC_RX_D_P -> PLL( the output frequency is same as the input, adjusting the phase ) -> LVDS12401 -> DCFIFO  --- Quote End ---     we already talked about that in this thread.. making a timing constraint file to do that phase shifting "expectation".. in order to tell fpga what to expect from ADC.. how much degree of phase shift is data with respect to clock.   Michael

[Altera_Forum]

--- Quote Start ---    Dynamic phase shift is a basic feature of the PLL blocks since Cyclone III. It can be used to achieve a DPA-like functionality with the LVDS PLL, but not for individual bits. Unlike with hardware DPA, that can be simply enabled in the MegaWizard, you have to design the phase shift state machine and signal edge detector yourself.    --- Quote End ---     how hard do you think this can be for a newcomer like me?

[Altera_Forum]

I had a similar ADC only two channels in offset mode 12-bit 80 MSPS. I didn't use the lvds module, but the DDR input megafunctions. The important thing to remember is that this megafunction, which is also in the lvds megafunction, delays your data by one full data clock. This means that if you use both the frame and data clock from your ADC you have to shift your frame clock over by at least one data clock. From here you can do timing reports and continually adjust the frame clock time shift until you get the best results. 

 The following SDC worked for me and I've had no timing issues what so ever.  # # VERITUAL CLOCK FRAME# # create_clock -name fpga_clk_frame -period "40MHz" # # VIRTUAL CLOCK DATA# # create_clock -name ext_clk1 -period "240MHz"# # INPUT CLOCK WITH 90 DEGREES PHASE SHIFT create_clock -name fpga_clk_data -period "240MHz" -waveform {1.042 3.125} set_input_delay -clock ext_clk1 -max 0.250 }] set_input_delay -clock ext_clk1 -min -0.250 }] set_input_delay -clock ext_clk1 -max 0.250 }] -clock_fall -add_delay set_input_delay -clock ext_clk1 -min -0.250 }] -clock_fall -add_delay set_input_delay -clock ext_clk1 -max 0.250 }] set_input_delay -clock ext_clk1 -min -0.250 }] set_input_delay -clock ext_clk1 -max 0.250 }] -clock_fall -add_delay set_input_delay -clock ext_clk1 -min -0.250 }] -clock_fall -add_delay set_input_delay -clock ext_clk1 -max 0.250 }] set_input_delay -clock ext_clk1 -min -0.250 }] set_input_delay -clock ext_clk1 -max 0.250 }] -clock_fall -add_delay set_input_delay -clock ext_clk1 -min -0.250 }] -clock_fall -add_delay set_input_delay -clock ext_clk1 -max 0.250 }] set_input_delay -clock ext_clk1 -min -0.250 }] set_input_delay -clock ext_clk1 -max 0.250 }] -clock_fall -add_delay set_input_delay -clock ext_clk1 -min -0.250 }] -clock_fall -add_delay set_false_path -setup -rise_from -fall_to set_false_path -setup -fall_from -rise_to set_false_path -hold -rise_from -rise_to set_false_path -hold -fall_from -fall_to

[Altera_Forum]

Hi Lewy0701, just wondering if you have succeeded in designing your project? If yes, would you mind sharing with me? Thanks