Hi,I am using the Output DDR interface in one of my submodules in the hierarchy. I see that the output register is not set in spite of me selecting the option "Registers powerup high". Also, I see that the data is being passed from input to output of the primitive even though, outputclocken is low. Is the IP only to be used when the output of the same directly drives the output pin? Can it be used in internal modules whose output drive some internal signals in the next level of hierarchy If no, Is there any alternate primitive to help me achieve the same? If yes, could you please tell me why I see this behavior? Your help is appreciated. Thanks, Vittal
This is meant to map to the IO cell DDR registers, and my experience is that it errors out if not hooked up to an output port. You should be able to do the same in RTL very easily. The main purpose is to make sure it uses the dedicated resources, especially the output mux, which inference tools have never been great at(not that it would be hard).
Thanks.Yes, I used a custom RTL block and everything works well now. Just curious - It does not throw out an error (or even a warning) when I use ODDR2 in the submodules. I have used ODDR2 (in submodules) using different (non-altera) FPGA design tools before, and it works fine there. A warning or error regarding this would have been better. Thanks, anyway!
If it works, that's great. Note that some devices don't actually have DDIO, so when you put this down it gets done in logic, so maybe that's what is occurring. If it doesn't error out and synthesizes to something functionally wrong, then it's a problem, but if it works inside, great.
Sorry if I explained it wrong. What I meant was that I removed the ODDR buffer and wrote one on my own.You are right, the ODDR buffer if used internally gives a functional error (although the synthesis tool does not see that and does not throw out any errors/warnings). Bottom line - ODDR2 in cycloneV does not work inside.