ALTIOBUF - Enable input buffer dyamic delay chain

[Mikexx]

I get a series of errors when this feature is ticked in the ALTIOBUF:

Cyclone V

Quartus 20.1

Error (129036): Output port DATAOUT on atom "DQS_Diff_4:u_DQS_Diff_4|DQS_Diff_4_iobuf_bidir_3qg1:DQS_Diff_4_iobuf_bidir_3qg1_component|sd1", which is a cyclonev_delay_chain primitive, is not connected to a valid destination
Info (129025): Output port DATAOUT of atom "DQS_Diff_4:u_DQS_Diff_4|DQS_Diff_4_iobuf_bidir_3qg1:DQS_Diff_4_iobuf_bidir_3qg1_component|sd1" is driving the I input port of atom "DQS_in[0]~output", which is a cyclonev_io_obuf primitive
Info (129038): Input port DATAIN of a cyclonev_ddio_in primitive is a valid destination for output port DATAOUT on atom "DQS_Diff_4:u_DQS_Diff_4|DQS_Diff_4_iobuf_bidir_3qg1:DQS_Diff_4_iobuf_bidir_3qg1_component|sd1"
Info (129038): Input port D of a cyclonev_ff primitive is a valid destination for output port DATAOUT on atom "DQS_Diff_4:u_DQS_Diff_4|DQS_Diff_4_iobuf_bidir_3qg1:DQS_Diff_4_iobuf_bidir_3qg1_component|sd1"

If this feature is not ticked the design compiles successfully.

I have added two archived projects demonstrating the issue:

  DQS_Test_1 : With Enable ticked

  DQS_Test_2 : With Enable unticked

Where am I going wrong?

[EthanLi]

Hi,

This is Ethan from Intel AE team.

I have checked your design and find that the data_out(DQS_in) from the input delay chain connected directly to the output pin in the top design. Once you use the delay chain you should not connect the data_out of the delay chain to the output port of the top level directly, you may connect the data_out to the input of fifo or ddio etc.

I will upload the design compiled successfully.

Thanks,

Ethan

[Mikexx]

Many thanks for looking into this.

The intent was to delay the DQS inputs by a small amount and to use this internally within the FPGA rather than feeding a DDR IO primitive.

Although the projects were a cut-down of the original project, the intent was to drive the DDR clock in signal with DQS_in to convert the DDR data into SR data.

The datasheets for LPDDR memory suggest that it is the DQS signals that should be delayed to match the DQ data valid time, hence my approach.

[EthanLi]

Hi,

I think if you merge it to the whole design, there will be no compile error even it is not fed to DDR.

Have you tried the merged design ever?

Thanks,

Ethan

[Mikexx]

Sorry for the long delay and many thanks for the design.

I think the best thing to do here is upload the IOE structure and explain I am trying to adjust the following delays:

D1

D3_0

D3_1

D4

It's not obvious or intuitive how this is accomplished with the io_config_**** signals in the ALTIOBUF primitive.

Are there any examples?