Can anyone tell my why ALTLVDS_RX with an external PLL requires;1 clock at data_rate/2 when using Quartus 13.1 1 clock at data_rate + 1 clock at data_rate/deser-factor when using Quartus 16.1 This is annoying.
What device are you using(and if it has True LVDS, are you using it), and what's the deserialization factor(deser of 2 does not use true LVDS but DDIO structure, and runs much slower). What speed?Never fully trusting myself, I generate an altlvds with internal PLL, then go to the Fitter Report's PLL Usage and see what the clocks are doing, and make my external PLL do the same. If you post that here we might be able to shed some light.
Thanks for the response.I'm using Cyclone V with true LVDS, 8 bit deserialization, 320Mbits/s data rate. In my post I just reported what the MegaWizard GUI was telling me. A single clock is required for Quartus 13.1, and two clock are required for Quartus 16.1. I'm guessing Altera simply redesigned this IP and changed the way it operates.
True LVDS uses dedicate silicon in Cyclone V, so it shouldn't be redesigned. In both cases the PLL should have three outputs:c0: This is the high-speed clock that runs at the serial rate and clocks in the data. (True LVDS does not use the DDR registers. Instead, it captures with a single register running at the full rate, thereby avoiding any issues due to rise/fall variation on the clock tree) c1: This is an enable bit for loading this serial data into a parallel register. That is why it's duty cycle is 1/8th the clock period c2: This is your core clock, with a 50% duty cycle, that runs at the parallel data rate. Please look at the following: https://www.altera.com/support/support-resources/knowledge-base/solutions/rd06142011_962.html Hopefully that helps.
Thanks. I get it. But it doesn't address my original question, why the difference between Quartus 13.1 and 16.1? To me it means that if I want to compile my older project on a newer tool, I have to change the design.
I did not think that was the case. Again, the hard IP is the same. I opened both versions, launched altlvds_rx megawizard/qsys for Cyclone V, made the deser /8, clicked on external PLL and they both say the same thing. Can you copy the two messages your looking at here and also put where they're coming from?I think there are multiple ways to do it as long as the relationship stays the same. I'm almost postiive the frequencies must be the same between versions(one fast, one parallel, and one parallel with small duty cycle for enable)
Are you sure the first picture is targeting Cyclone V? When I launch Q13.1 and create altlvds_rx /8 with external PLL, I get the exact same text as your second one. If I change it to Cyclone IV(or any device that doesn't have True LVDS), then I get the text in your first picture.Also note that your first screenshot only has one clock coming in, where True LVDS needs two. And the clock rate it talks about is /2 the data rate, which is exactly what the clock should be if you don't use True LVDS and instead build it out of a DDR input register. So I'm pretty certain the second screen shot is doing True LVDS while the first one is not, and instead building it out of DDR input registers. I'm not quite sure why though, but it shouldn't be a 13.1/16.1 issue. If you have further problems, please include the 13.1 output .v/.vhd file and I can open it in Q13.1. (Perhaps the option to match project is checked and the project is CIV, while the greyed out option above it says CV?)
You are correct, and I offer my sincerest apologies if I wasted your time. I didn't realize the Q13.1 design was targeting the Cyclone IV, as you correctly deduced.