ALTLVDS rx timing issue

[kikoss]

Hello I have hold timing issue on the ALTLVDS RX  inside logic .. 

I have an ALTLVDS RX ip confgiured like that

i get hold timing issues in timequest : 

-0.019 u_tx_rx_wrapper|u_adc_controller|lvds_0|core|arch_inst|rx_channels[1].dpa_fifo.serdes_dpa_inst~rx_internal_reg u_tx_rx_wrapper|u_adc_controller|lvds_0|core|arch_inst|rx_channels[1].dpa_fifo.des[4].rxout_ufi~ufi_write_reg u_tx_rx_wrapper|u_tx_rx_pll|iopll_0_fclk0 u_tx_rx_wrapper|u_tx_rx_pll|iopll_0_loaden0

why its occur ?  its inside the altera IP .. 

Thx 

kikoss 

[AqidAyman_Intel]

Hello,

May I know what is your input clock frequency?

[kikoss]

Hello 

the input clock frequency is 96Mhz 

Thx

[AqidAyman_Intel]

Hello,

Thank you for your confirmation. Does it come from the dedicated reference clock pin within the I/O bank?

Which device is this and you are using which version of Quartus Prime?

Regards,

Aqid

[AqidAyman_Intel]

Hello,

I wish to follow up. Do you have any update?

Regards,

Aqid