ALTLVDS rx timing issue

[kikoss]

Hello I have hold timing issue on the ALTLVDS RX  inside logic .. 

I have an ALTLVDS RX ip confgiured like that

i get hold timing issues in timequest : 

-0.019 u_tx_rx_wrapper|u_adc_controller|lvds_0|core|arch_inst|rx_channels[1].dpa_fifo.serdes_dpa_inst~rx_internal_reg u_tx_rx_wrapper|u_adc_controller|lvds_0|core|arch_inst|rx_channels[1].dpa_fifo.des[4].rxout_ufi~ufi_write_reg u_tx_rx_wrapper|u_tx_rx_pll|iopll_0_fclk0 u_tx_rx_wrapper|u_tx_rx_pll|iopll_0_loaden0

why its occur ?  its inside the altera IP .. 

Thx 

kikoss 

[AqidAyman_Intel]

Hello,

May I know what is your input clock frequency?

[kikoss]

Hello 

the input clock frequency is 96Mhz 

Thx

[AqidAyman_Intel]

Hello,

Thank you for your confirmation. Does it come from the dedicated reference clock pin within the I/O bank?

Which device is this and you are using which version of Quartus Prime?

Regards,

Aqid

[AqidAyman_Intel]

Hello,

I wish to follow up. Do you have any update?

Regards,

Aqid

[kikoss]

Hello sorry for the delay 

i was in vacancy 

the quartus version is quartus prime 24.1

yes the clk is dedicated clock : BANK 2F  pin DD47

Thx 

[AqidAyman_Intel]

Apologies not asking this earlier. Which device does this LVDS IP target? 

[kikoss]

Hello targeting the agilex7 f series : AGIB027R31B1E1V 

[AqidAyman_Intel]

Hello,

We have tried creating an example design with the parameters shown and saw no timing failures. The worst-case slack for the timing path listed was 2.853.

The large discrepancy between the slack we are seeing and the slack you are seeing is mostly likely due to you having a different clock relationship because their PLL clocks are configured incorrectly.

Ensure that the VCO frequency and the outclk frequency/phase shift/duty cycle settings on the external PLL driving the LVDS IP match the settings listed in the Clock Resource Summary in the LVDS IP.

Also, please ensure that the reference clock frequency on the PLL IP matches the Actual inclock frequency on the LVDS IP as the settings listed in the Clock Resource Summary tab may not be attainable with the wrong reference clock frequency.

Regards,

Aqid

[AqidAyman_Intel]

If it’s not caused by incorrect clock configuration, other possible causes include using an outdated SDC due to using an old Quartus version (19.2 or older) or a placement/routing issue.

[kikoss]

I dont see any issue on the design ... iam using : quartus prime 24.1 .. 

any idea ? 

[kikoss]

I reduce my design to the minimum.

And seems that the issue occurs when we choose more than 2 channels 

when running with 2 channels, no timing issue, when running with 3 channels, I get hold time issue ... 

@AqidAyman_Intel  seems there its an altera issue .. 

wait for help from @altera  .. 

THX 

kikoss

[kikoss]

to be more precise : the issue occur when we have at least 3 channels and when the pll is external one  .. 

[AqidAyman_Intel]

Hello,

I will contact you through email since I need to share with you some of the snapshots.

Need your help to check the inbox.

Regards,

Aqid