Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18983 Discussions

ALTPLL For Multiple Input Frequencies

BigSid
Beginner
428 Views

A design has a requirement for processing one of 65,536 different input frequencies. Using the  ALTPLL megafunction by itself requires specifying just one input frequency. Reconfiguring the ALTPLL will allow for handling a finite number of input frequencies. Any ideas on how to accommodate such a large number of potential input frequencies? Thanks. 

0 Kudos
7 Replies
EngWei_O_Intel
Employee
402 Views

Hi @BigSid 

 

There is clock switchover features in certain variant of devices but I believe still not sufficient to accommodate 65k different frequencies. Looks like reconfiguration is the way to go. May we know how you want to use these different clocks in your design?

 

thanks.

Eng Wei

BigSid
Beginner
391 Views

Hello. 

The design has 65,536 discrete input frequency values, ranging from 50kHz to 450kHz. The ALTPLL minimum input frequency is 5MHz, correct? If so, do any frequency multiplication megafunctions exist (I'm using a Cyclone III device but will upgrade if necessary) to allow for increasing this range so that it's above the 5MHz minimum before being input into an ALTPLL? If not, I'll add a clock multiplier outside the FPGA first and divide by an equal scale in the ALTPLL to restore the 50kHz to 450kHz range.

 

The goal is to use ALTPLLs (with reconfiguration) to generate six output clocks at specified phases with respect to the input clock. I've found an example in the literature (see Figure 7 attachment) that shows three ROMs being created to allow for selection from one of three different input frequencies. I have 65,536 different input frequencies. Is there a way to achieve this without creating 65,536 ROMs?

 

Thanks.

 

 

 

EngWei_O_Intel
Employee
376 Views

Yes you are right. The minimum freq for PLL refclk in Cyclone III device is 5MHz. 

 

There are methods for PLL reconfiguration:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an507.pdf

 

Thanks.

Eng Wei

BigSid
Beginner
356 Views

Design Example 1 in AN507 shows the PLL being reconfigured with one of three .mif files used to select output frequency. Is there a way - other than manually generating 65,536 .mif files - to achieve what I'm looking to do? Thanks.

EngWei_O_Intel
Employee
322 Views

Hi @BigSid  

 

You can also reconfigure the PLL according to method 1 in

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an507.pdf

 

Thanks.

Eng Wei

EngWei_O_Intel
Employee
301 Views

Hi @BigSid 

 

I am transferring this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

 

Eng Wei

GLees
New Contributor I
286 Views

I have found that the PLL lock range can be as great as 2:1, so you probably don't need 65535 reconfigurations.  Maybe only 4-8 are required.

Reply