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Honored Contributor I
998 Views

ALTPLL for multiple input frequencies

Hi All, 

 

I have an input clock to MAX-10, which could be 2.5MHz, 25MHz, and 250MHz.  

 

I need to put a PLL on this input clock (for shifting the input clock by 90 degrees).  

 

I don't have any indication what clock (frequency) is currently connected to the pin.  

 

So, how should I configure the ALTPLL? What frequency should I define? What Mode (normal, clock synchronous, etc).  

 

Thank you!
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Honored Contributor I
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Altera PLLs have a maximum lock range of about 1:2. Also constraints for PFD frequency range.  

 

Changing input frequency over a wider range would require PLL reconfiguration or multiple PLLs. Also input frequency of 2.5 MHz is below specified MAX10 range.
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Honored Contributor I
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If you can design some logic for determining which of the three frequencies is present, you can dynamically reconfigure the PLL to work with that frequency.

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Honored Contributor I
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Hi, gj_leeson! 

 

I have the same problem: on one pin may be clock 25MHz or 125MHz and I have a pin, which indicates this - 0 for 25 and 1 for 125. 

I read altera manuals about altpll_reconfig with several mif-files. I create the same scheme with two ROMs, MUX, pll_reconfig and pll. I create two mif-files from pll wizard for two input clocks. 

And my question: how should I configure the pll? The default PLL settings are for 125MHz, because this situation is more difficult for scheme and TimeQuest timing analyzer. Am I right or not? 

What would you advise in this case? 

 

Thanks!
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Honored Contributor I
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125Mhz default sounds correct.

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