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Altera_Forum
Honored Contributor I
1,446 Views

ALtera MAX10 JTAG Problem

Hello, 

I made some BLDC and IO expander boards based on Altera MAX10, and i have strange problem that from Quartus at first programming after power was supplied, it does not want to program, but second time and for the rest of debugging session, it works first time (I.E just first JTAG sessionis failing, rest of them working every time without fail) . This is very strange behavior i noticed with all of my MAX10 Boards. 

 

What pushed me to make this thread is that new boards that i made take this effect to the next level. From second try to 20-30 tries Altera does not want to be programmed, but then again, just then i get first successful code loaded to FPGA (just to Altera, not to internal flash so it can boot on it's own) it start to work as it should, every other data loading to MAX10 works from that moment on, until next power-up. 

 

Any idea why it can be happening ? 

 

This is my JTAG for MAX10.
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9 Replies
Altera_Forum
Honored Contributor I
177 Views

So my idea why it is failing is because of slow ramp for power supply. Now in datasheet it says that ramp time must be faster than tRAMP, but no mention how large tRAMP can be, that is good job altera/Intel. 

 

So by the looks of it, this is what happens: 

 

" If the ramp time, tRAMP, is not met, the MAX 10 device I/O pins and programming registers remain tristated, 

during which device configuration could fail." 

 

Question is, how can i overcome this problem, i mean, what should i do to get into programming after i get init fail ? pulling nConfig low does nothing when i get fault condition, only cycling power is letting Altera to boot ( doe to higher ramp speed )
Altera_Forum
Honored Contributor I
177 Views

Hi,  

 

tRAMP time can be found in MAX10 device datasheet which is 10ms max. I am guesing that you were expecting to found this value in "Power Management User Guide". 

 

Which device do you use? Single-Supply or Dual-Supply device? 

Measure your tRAMP time and make sure that all required power supply rails are properly connected.
Altera_Forum
Honored Contributor I
177 Views

my fast slope is 20ms to get to 2v, and then slow part of the ramp is 100ms to get to 3.3V 

 

I am using TPS7A8101 for 1.2V and 3.3V generation, and LT3042 for 2.5V generation. So what, i am screwed because my LDO can 't get into 3.3V and 2.5V and 1.2V in 10ms ? WTF 

Device is MAX10 10M16DAF256C8G 

 

Also i am generating 5V from LTM8022V, and use it's power_good to start all my LDO converters. so i only start LDO when i charge my main 5V capacitors. This should prevent low ramp speed. But damn, that was still no
Altera_Forum
Honored Contributor I
177 Views

As i understand you are using JTAG chain to programm it. If I am correct only device boot process from its internal flash could fail if tRAMP is not met. tRAMP time should take no effect when using USB blaster to programm it with quartus software.  

 

1. Check nSTATUS pin that it goes high after power up.  

2. What programmer do you use? I had similar situation with Terrasic USB blaster, sometimes it failed to programm from first try.  

3. There should be some error codes in quartus when programming fails. What does it say?  

4. Can you provide schematic part of power supply connection at MAX10 device side? I will take a look if there are no errors.
Altera_Forum
Honored Contributor I
177 Views

1) nSTATUS does go high after power on, even if device is fail to boot from flash 

2) Yes, it is Terrasic USB blaster programmer. Strangely enough, when device does not boot, jtag still can't find it, while all voltages are spot on within 5mV. but when i cycle power, and max10 booted, it can be programmed first time every time. 

3) No errors, it can't find any device in JTAG chain. 

4), yes i can ( goto circuit.pdf) ( Note i changed VCC_3.0V to 3.3V since i was thinking that was a problem, but in the end, not)
Altera_Forum
Honored Contributor I
177 Views

From quick review of your schematic did not find any obviuos errors. But here is some errata related to Max10 configuration failure: 

https://www.altera.com/en_us/pdfs/literature/es/es_max10.pdf (https://www.altera.com/en_us/pdfs/literature/es/es_max10.pdf

 

For now I am out of ideas what could be wrong. Have you tested your terrasic download cable with other boards?
Altera_Forum
Honored Contributor I
177 Views

Thank you for trying. My old batch of same boards worked, and this one does not. I guess i will try to use old batch FPGA's, since i am out of ideas. 

 

It is crazy that MAX10 needs 10ms pover startup time, this is unreachable by 99% of LDO's as well as dc/dc converters. not good. Or do i am missing something ?
Altera_Forum
Honored Contributor I
177 Views

I think it is easy to find regulator with start-up-time less than 10ms. 

Check this regulator TLV702 from ti and EN6360QI from Altera.
Altera_Forum
Honored Contributor I
177 Views

Now i see, that many low noise LDO wired in low noise mode suffers from slow turn on time, because they use Noise Reduction capacitor that acts as RC filter for reference, and thus generating slow ramp time. Removing NR capacitor to 20x smaller made my boards work again. So yes, i must get 5ms turn on if i want my boards to work at all