Community
cancel
Showing results for 
Search instead for 
Did you mean: 
GDeXi
Beginner
262 Views

AN477 Question

Jump to solution

 Hello,  I just  feel strange with AN477 doc below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an477.pdf

page 12

Screenshot from 2020-09-17 17-50-01.png

 why the

      Calculated output maximum delay =  tsu of external register = –0.9 ns

 is not -tsu of external register ? 

 or  = 0.9 ns ?

 

 thanks for your help

0 Kudos
1 Solution
KennyT_Intel
Moderator
252 Views

This is because


1) The multicycle assignments are used to create a setup relationship of 0ns and a hold relationship of -1/2*period.

2) The value for set_output_delay -max is now negative due to the 0ns setup relationship set by the multicycle then the setup requirement (max data delay).



View solution in original post

6 Replies
KennyT_Intel
Moderator
253 Views

This is because


1) The multicycle assignments are used to create a setup relationship of 0ns and a hold relationship of -1/2*period.

2) The value for set_output_delay -max is now negative due to the 0ns setup relationship set by the multicycle then the setup requirement (max data delay).



View solution in original post

244 Views
Listening to you is better than reading ten years!!! Thanks。

GDeXi
Beginner
237 Views

Sorry, 

I have thought for a long time, but I still don't understand. Could you describe it in detail? thank you

 

KennyT_Intel
Moderator
214 Views
KennyT_Intel
Moderator
198 Views

Any update?


184 Views

For personal reasons, I'm sorry to reply you so late. 

For AN411,I have read page 32.

I can understand why Multicycle set , for same edge launch and latch. I don't  understand why max data delay now is negative.  

Q1: 

   i don't understand max data delay is negative has some related to Multicycle. and why data delay is negative.

Q2: 

  Is it analyzed according to this formula? 

 ddd.png

 

I'm sorry for the trouble!

Have a good day.

 

 

 

Reply