(AN741) Nios cannot erase on-chip FLASH

[jpark198]

I try to test RSU. I make .pof with my FPGA design and remote_update.c in AN741.

but when i try to update image 2, it doesn't work.

I type start address and end address and it is correctly work.

case 7: /*State 7: Write Control Register of On-Chip Flash IP to un-protect and erase operation*/
IOWR(MAX10_FLASH_CSR_BASE, 1, 0xfbffffff);
IOWR(MAX10_FLASH_CSR_BASE, 1, 0xfbcfffff);
state++;
break;

this part is not work and the system was freeze.

and i use UART(RS-232). not JTAG UART.

what is problem?

it is my tools information

-Quartus Prime 17.0 Lite

-DE10-Lite Board

[jpark198]

I found out where the problem is.

When I try to delete CFM1, the following codes are executed in order.

======================

case 5: /*State 5: Write Control Register of On-Chip Flash IP to un-protect and erase operation*/
IOWR(ONCHIP_FLASH_0_CSR_BASE, 1, 0xfdffffff);
IOWR(ONCHIP_FLASH_0_CSR_BASE, 1, 0xfdbfffff);
state++;
break;

case 6: /*State 6: Start erase CFM1*/
if((IORD(ONCHIP_FLASH_0_CSR_BASE, 0) & 0x13) == 0x10)
{
IOWR(ONCHIP_FLASH_0_CSR_BASE, 1, 0xfbffffff);
printf("CFM2 Erased\n");
state++;
}
if((IORD(ONCHIP_FLASH_0_CSR_BASE, 0) & 0x13) == 0x01)
{
//printf("Erasing CFM2\n");
}
if((IORD(ONCHIP_FLASH_0_CSR_BASE, 0) & 0x13) == 0x00)
{
printf("Erase CFM2 Failed\n");
state=20;
}
break;

case 7: /*State 7: Write Control Register of On-Chip Flash IP to un-protect and erase operation*/
IOWR(ONCHIP_FLASH_0_CSR_BASE, 1, 0xfbffffff);
IOWR(ONCHIP_FLASH_0_CSR_BASE, 1, 0xfbcfffff);
state++;
break;

=============

However, the code was in an infinite loop in case 6. The value of 'IORD(ONCHIP_FLASH_0_CSR_BASE, 0) & 0x13' was 0x03, which means busy.

In addition, it was confirmed that the writing of the register to be executed in case 5 was not working properly.

IOWR(ONCHIP_FLASH_0_CSR_BASE, 1, 0xfdffffff); <-(1)
IOWR(ONCHIP_FLASH_0_CSR_BASE, 1, 0xfdbfffff); <-(2)

The result of checking the result values for these two commands was as follows.

Register value before executing (1): 0x3fffffff

Register value before executing (1): 0x3fffffff

Register value before executing (2): 0x3fffffff

I could confirm that (2) was not working properly. I want to know how to solve the current problem.

[EricMunYew_C_Intel]

Hi, Junbum

Can you check two things whether you do it correctly:

1. the start and end address can be found in the Altera on-chip flash IP.
2. the baud rate, number of data bits, parity etc must be matching in your JTAG IP.

You may refer to page 13 and 14 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an741.pdf

Eric

[jpark198]

There was no problem with the mentioned matters.
Even if adress was set to a constant value, the flash was not erased as well.

[EricMunYew_C_Intel · Accepted solution]

Hi, Junbum

You can find the start and end address of CFM1 (for your application image) in the .map file when you generate the .pof. 

You need to copy and paste the block with above start and end address into a new .rpd (for the application image to be updated remotely). But in newer Quartus versions, you don't have to do that, there is a .rpd automatically generated for CFM1.

You need to create a quartus.ini in your project directory, and put below line in it, before you do covert programming file to .pof from your application .hex.

PGMIO_SWAP_HEX_BYTE_DATA=ON

Eric

[EricMunYew_C_Intel]

Hi, Junbum

Do you have any more inquiry ?

Eric

[jpark198]

I was able to partially solve this problem apart from the previous answer. When using Interval Timer in QSYS, the above error occurred. And when deleting Interval Timer, it was confirmed that Remote System Update can be used normally. I want to know how to solve these problems.

And i use Quartus Prime Lite Edition 17.0

[EricMunYew_C_Intel]

Hi, Junbum

I find there is no interval timer in the AN741 reference design.

May I know where the interval timer coming from ?

Eric

[jpark198]

That's what I added because I needed it. In the application I want to use, I added the Interval Timer along with SPI, UART, and GPIO, so they all worked normally. And when I tried to add RSU function to my design, a problem occurred in Interval Timer.

[EricMunYew_C_Intel]

Hi, Junbum

Can I close this first as this has been long overdue ?

You can open a new case to follow up on the interval timer.

Thanks.

Eric

[EricMunYew_C_Intel]

Hi, Junbum

You can open a new thread for the interval timer.

Thanks.

Eric