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ARM cache coherency

Altera_Forum
Honored Contributor II
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I have just joined a team of engineers working on an ARRIA 10 design with the HPS. 

 

The FPGA fabric has several interfaces that DMA their data into the HPS DRAM via a FPGA to HPS bridge. We are seeing many issues of data corruption which I am convinced is a cache coherency problem. 

 

I am trying to figure out exactly what sort of cache the ARM uses (write through? Write back? Snooping?) but I am just getting myself confused. I see mention of a 'system register' where the type of cache would get written. Is this programmable? Is there a standard default? 

 

The AXI bus has the four bit field AWCACHE. It appears that the system currently designed here is setting these four bits to zero. I am not sure, but I think that is the least likely to work value. I have seen other references where all ones (4'b1111) is good. But then does the setting of that System register need to match? 

 

Is there an Altera Reference design that has a DMA module in the FPGA fabric to the FPGA to HPS bridge that I can use as a starting point here?  

 

Thanks 

 

Rod 

 

One more question: How big is a cache line on the ARM?
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