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ARRIA 10 Bidir GPIO Synthesis error

empissas
Beginner
204 Views

Hi ,

 

I  try to instantiate a tri-state buffer using the GPIO IP CORE . Although  i assume that i had made all the connection correct the  synthesis stage outcomes this error

 

Error(17044): Illegal connection on I/O input buffer primitive i2c_test|gpio_0|core|i_loop[0].altera_gpio_bit_i|input_buffer.ibuf. Source I/O pin i2c_test|pad_io[0] drives out to destinations other than the specified I/O input buffer primitive. Modify your design so the specified source I/O pin drives only the specified I/O input buffer primitive.

The connections that i had in the top level design are the following

inout wire tri_buff;

i2c_bidir u0 (
.dout (),
.din (), 
.oe (),
.pad_io ( tri_buff) 
);

the tri_buff signal does not drive any other destination and i cannot understand why the above error occurs

 

Thanks in advance

 

 

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6 Replies
sstrell
Honored Contributor III
171 Views

Strange.  Anything unusual about the pin you selected for this in Pin Planner?

empissas
Beginner
156 Views

No, nothing unusual.  I assume that the pad_io  signal has to be assigned an inout top level pin in order to connect to the pad . Is that right?

sstrell
Honored Contributor III
135 Views

I believe so.  Does it show as bidirectional in the Pin Planner All Pins list?

Oh, since you can't synthesize, you might not even be able to do that.  Hmm.

Is the first stage of synthesis, Analysis & Elaboration, successful if you run it on its own?

empissas
Beginner
127 Views

I finally found why the synthesis stage had this error.

 

 

Thanks

sstrell
Honored Contributor III
119 Views

So for future reference, what was the problem?

empissas
Beginner
108 Views

I had also  set this bidir pin as signal in the signal tap logic analyzer. This way, the synthesis stage assumed  that is was driving more than one destinations.

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