I have an Arria10 design which includes an ATX PLL. The design operates properly on most boards but on about 10% of boards the ATX PLL never exits calibration ( i have verified the frequency of the refclk on chip as well as all voltages). I am basically fishing for anyone who has seen this behavior and what they found to be the root cause of their problem as that may apply here as well.
As I understand it, Andy seems to have helped open an IPS case on this. I have responded to the IPS especially on the CLKUSR requirement. Please let me know if you would require further clarification. Thank you.
