Hello, I would like an IP that I can program a start address from an SoC's CPU address space and a length, and the IP will read the memory via AXI-4 and generate AXI4-Stream data transactions as it is allowed by downstream tready. Xilinx has an AXI-DMA IP for this. What is Intel's solution? I have not been able to identify a canned solution on this platform with this capability.
Can you mention which device you are targeting.
There is AXI-Bridge IP available , if you look in the Qsys. Can you try with the AXI-Bridge and let us know.
But there is no AXI streaming IP is available with us, But memory mapped solutions are available.