Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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About PCIE problems

drli
Beginner
524 Views

I design a board using FPGA Arria 10AX016E4F27E3SG serving as an endpoint in PCIE 2.0. The board communicates with the PCIE switch plugged on PC's PCIE slot through fiber and SFP+ optical module. When I adopt an A manufacture optical module, the communication is OK. However, when I adopt a B manufacture optical module, the PCIE device on FPGA can be detected on PC, but the Bar space cannot be allocated. Both A and B optical module are mass production optical module and may be  a little difference. How can I debug this problem due to the communication on FPGA cannot signaltap the physical signal directly due to the hardIP of FPGA? Thank you !

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wchiah
Employee
452 Views

Hi,


I suggest you to try use logic analyzers to capture and analyze digital signals in your design. This can help you identify issues with signal timing or protocol compliance.


Hope that helpful.

Regards,

Wei Chuan


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wchiah
Employee
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Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

 

Regards,

Wincent_Intel


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wchiah
Employee
366 Views

Hi

 

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

 

Regards,

Wincent_Intel


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