About path delay in my FPGA

[Altera_Forum]

My dear, 

My application is that a signal EN_in to my FPGA , and a EN_out from my FPGA to ADCs. Now I want to delay the signal for unknown ns to need the ADC timing,the detail ns is test by my teamer. So I set some deifferent paths and a probe IP in my design,so my teamer use the probe IP to select the best delay path to use. -------------------------------------------------------------------------------- my design(.v):  input EN_in; output EN_out;  (* keep *) wire EN_delay0; (* keep *) wire EN_delay1; (* keep *) wire EN_delay2; (* keep *) wire EN_delay3;  assign EN_delay0 = EN_in; assign EN_delay1 = EN_in; assign EN_delay2 = EN_in; assign EN_delay3 = EN_in; assign EN_out = (probe==2'b00) ? EN_delay0 : ((probe==2'b01) ? EN_delay1 : ((probe==2'b10) ? EN_delay2 : EN_delay3)); -------------------------------------------------------------------------------- my constraint(.sdc):  set_min_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay0}] 1.000 set_max_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay0}] 2.000 set_min_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay1}] 3.000 set_max_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay1}] 4.000 set_min_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay2}] 5.000 set_max_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay2}] 6.000 set_min_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay3}] 7.000 set_max_delay -from [get_ports {EN_in}] -to [get_cells {EN_delay3}] 8.000 --------------------------------------------------------------------------------  But,but...but...I found that 4 delay paths not work efficiently... There is just 570ns between The Max delay path and The Min delay path . And the min delay path isnot EN_delay3 . My FPGA is EP4SGX230KH40. Help me. Thanks all.

[Altera_Forum]

You can't use timing constraints (set_min/max_delay) to add delay to your output signals. That's not what they're used for. 

 If you really want to stagger 8 signals with a 1ns delay between them you'd need a 1GHz clock.  Cheers, Alex

[Altera_Forum]

You might be able to use an fPLL available in newer FPGA families - but not Startix IV. 

 Cheers, Alex