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Valued Contributor III
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Active Parallel Configuration at less than 40MHz, is it possible?

The Altera website states that: 

 

 

"You can perform active parallel (AP) configuration using a supported common flash interface (CFI) parallel flash memory. During AP configuration, the Altera® device is the master and the parallel flash memory is the slave. Configuration data is transferred to the Altera device on the DATA[15:0] pins. This configuration data is synchronized to the DCLK input. Configuration data is transferred at a rate of 16 bits per clock cycle. The DCLK frequency driven out by the Altera device during AP configuration is approximately 40 MHz.  

For more information, please refer to the configuration chapter of the relevant Altera device in the Configuration Handbook. " 

 

 

 

And... 

 

 

 

"The Active Serial (AS) configuration scheme is supported in the 1 bit data width (AS x1) or the 4 bit data width (AS x4). The AS x4 scheme is supported only in Stratix® V devices. AS configuration can be performed using an Altera® serial configuration (EPCS) device or quad-serial configuration (EPCQ) device. During AS configuration, the Altera FPGA acts as the configuration master and the EPCS or EPCQ device acts as the configuration slave. The FPGA outputs the clock on the DCLK pin and receives the configuration data from the EPCS or EPCQ device on the data pin(s).  

For more information, refer to the configuration chapter of the relevant Altera device in the Configuration Handbook. " 

 

 

I assume that this means the flash memory must be a "CFI" flash, regardless of who manufactures it. Besides this, it seems to imply that the configuration can only occur at 40MHz and not any lower than that.  

My questions are: 

(1) Why is only a CFI flash required for AP configuration? What is deficient in non-CFI flash? 

(2) What is the frequency given as 40MHz? Certainly slower devices shall be cheaper and the amount of time it takes to configure the FPGA will not have changed drastically from human experience. 

(3) Why is only an EPCS and EPCQ device required for AS configuration? What is deficient in normal serial flash? 

 

 

On another note, which is the main reason for this question, 

(4) It is quite clear that the EPCS/EPCQ devices for serial configuration are mere flash devices yet cost significantly more than a "normal" flash device. Why is this so?
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Valued Contributor III
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In active configuration schemes the FPGA sources the clock. Depending on the device family, and potentially MSEL settings, this frequency will be fixed. So, any FLASH sourcing the data must be capable of operating at the stated active configuration speed for a given family. 

 

CFI FLASH only? Not necessarily. You could source your configuration data from another source - I've sourced the data for an AP scheme from a CPLD in the past. However, wherever you source the data from will have to keep pace with the given configuration clock frequency and timings. What 'non-CFI' device would you like to consider using? I'm not sure I'm aware of any... You'll have to be confident of a solution for programming it should the Quartus programmer not like it. 

 

As for AS schemes - no, you don't have to use Altera's own 'badged' EPCS/EPCQ devices. These are standard serial FLASH devices. Cheaper devices from (for example) Micron or Spansion (now Cypress) work perfectly well. Altera's own EPCS/EPCQ cost more simply because that's what Altera have chosen to do. 

 

Cheers, 

Alex
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Valued Contributor III
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I believe the more costly EPCS/EPCQ is justified since Altera provides full support if you are using the EPCS/EPCQ. If you are not that familiar with AS configuration and yet chose to use Micron or Spansion flash, then I believe Altera cannot support you with their technical support if you happen to run into some probs. BUT if you are confident enough, you can save yourself some money and just go for the cheap ones :)

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