Programmable Devices
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Active Serial Multi Device Configuration issue

ZKhan1
Novice
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Hi ,

 

I have a board with x02 Cyclone 10 Lp , part number : 10CL040YF484C8G , they are connected in Active Serial Multi Device config with first FPGA the master configurer . 

 

But the schematic designer made a mistake and now i have nCE, CONF_DONE and nSTATUS signals not connected to the 2nd FPGA .

 

Although CONF_DONE and nSTATUS are pulled high .

 

Will this issue cause the first FPGA not configured properly ? or will this issue make it remain in reset state ?

 

Regards ,

 

Thanks    

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AqidAyman_Intel
Employee
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Hi,


As far as I understand, you need to connect as per user guide if you are having multiple FPGA in Active Serial mode. If the configuration pin is connected wrongly, it will cause configuration error.


regards,

Aqid


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ZKhan1
Novice
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Hi Aqid ,

 

This is proto A PCB , yes you right it will be corrected in proto B PCB.

But i am thinking of ways to make it work , if possible as on the PCB i do have a separate flash connected to 2nd FPGA and i can program it without any problems .

 

But my question is there is PCB_RESET_n comming from 1st FPGA to the 2nd FPGA , and some processing happens after RESET in the 2nd FPGA , because of this hardware problem this RESET will not be asserted by the 1st FPGA .

Does this issue cause the configuration of the 1st FPGA to be NOT implemented / programmed at all , or it will always be in reset state . Because with the 2nd FPGA configuring with a separate Flash , their boot up time will be different .

Because in testing i do see some communication possible between the two FPGA's , but some times its failing ?

 

Regards , 

 

Ahmed  

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AqidAyman_Intel
Employee
616 Views

Hi Ahmed,


If based on the situation given, from my opinion, it will not affect the configuration on the first FPGA if CONF_DONE and nSTATUS signals not connected to the 2nd FPGA. Those two are dedicated configuration status pins.

According to the documentation, in a multi-device configuration, nCE of the first device is tied low while its nCEO pin need to drive the nCE of the next device in the chain.


Regards,

Aqid


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AqidAyman_Intel
Employee
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