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Add the serial ports of JESD204B to SignalTap, but compile failed.

CPaul10
Novice
336 Views

Hi,

 

Software:Quartus Pro Edition 20.4

Hardware:Intel A10 GX PCIE Kit

 

I would like to catch the serial ports of JESD204B by SignalTap.

But compile failed.

If I remove the serial ports(tx/rx) of JESD204B, it compiles successfully.

 

Failed Messages:

CPaul10_0-1637829342489.png

Pin assignment:

CPaul10_1-1637829440555.png

SignalTap:

CPaul10_2-1637829675898.png

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sstrell
Honored Contributor III
303 Views

I don't know anything about this IP, but it looks like you're trying to tap something that goes to I/O pins so it can't be both routed to the pins and routed to the core logic for the logic analyzer.  In situations like this, you should tap the internal signal that drives the register or logic that drives the pin.

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CPaul10
Novice
294 Views

Thanks, I'll try the register or logic.

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