Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Honored Contributor I
1,053 Views

Adding Hex numbers

Hi, 

Does anyone know how can I add Hex numbers inside the process (VHDL)?  

For instance, I want to add x"55" + x"55" but if I'll write " x"55" or x"55" " the answer will be x"55" (the answer should be x"AA"). 

Idan
0 Kudos
3 Replies
Honored Contributor I
93 Views

 

--- Quote Start ---  

Hi, 

Does anyone know how can I add Hex numbers inside the process (VHDL)?  

For instance, I want to add x"55" + x"55" but if I'll write " x"55" or x"55" " the answer will be x"55" (the answer should be x"AA"). 

Idan 

--- Quote End ---  

 

 

Of course x"55" or x"55" is x"55" as this is a binary or, used on the vector bitwise. 

 

Addition in VHDL (one of the reasons I prefer Verilog over HDL) requires type conversions as it has quite a strict type checking: 

result <= std_logic_vector(unsigned(x"55") + unsigned(x"55")); 

 

Also please note that unless you do know exactly what you do an addition of two vectors with N and M bits require the result to be max(N,M) + 1 bit wide.
0 Kudos
Honored Contributor I
93 Views

Thanks a lot...

0 Kudos
Honored Contributor I
93 Views

I want to add two hex numbers inside the process… 

This is my code: 

 

"  

LIBRARY IEEE; 

USE IEEE.STD_LOGIC_1164.ALL; 

--USE IEEE.STD_LOGIC_ARITH.ALL; 

USE IEEE.STD_LOGIC_UNSIGNED.ALL; 

USE IEEE.NUMERIC_STD.ALL; --I using "conv_std_logic_vector" function 

… 

signal TX_checkSum: std_logic_vector (8 downto 0); 

begin 

process (clk) 

begin 

if reset='1' then 

… 

elsif clk'event and clk='1' then  

TX_checkSum <= std_logic_vector(unsigned(x"55") + unsigned(x"55")); 

end if; 

end process; " 

 

I get the following error:" Error (10408): VHDL error at UART.vhd(139): can't determine type of object at or near string ""01010101"" -- found 25 possible types". 

What could be the problem?
0 Kudos