Dear sir,
i am using 5CEFA9F31C8(Cyclone V) in my design.
In the design, i need to receive lots of synchronous inputs from outside, for design rule limitation, i cannot use lvds_rx ip core, so i use ddio_in with a dynamic phase shift PLL to receive data. After compilation, TimeQuest Analyzer reported timing failure. I checked data arrival path of the failed path in the TA, and found that there was a large IC delay of 4.59ns in the path.
I searched the forum and found adding a pipeline register may help relieve this problem. so I inserted a pipeline register(e.g. pipeline_reg) in source code in the path with large IC delay(before inserting: ddio_out->data_reg; after inserting: ddio_out->pipelin_reg->data_reg), however, after compilation again, the large IC delay was still there, this time, the path with large IC delay was changed to between ddio_out and pipeline_reg than previous between ddio_out and data_reg, that is, adding a pipeline register did not relieve the problem at all.
I am not sure if i miss something.
Can you tell me how to reduce the IC delay. Is there any command to control the IC delay.
Thanks and Regards,
ingdxdy
