Addition Sum of Array

Altera_Forum · ‎07-18-2012

Hey @ all,

i'm new here and i have some questions about the Sum of an array (VHDL), that contains a lot of 8 bit value's of std_logic_vector.

For example i have declared the array as follow:

type table is Array (natural range <>) of std_logic_vector (7 downto 0);
constant vec_value: table := ("00000000","00000001","00000010","00000010","00000010","00000110","00010010");

Now i woult like to calculate the Sum of all elements of the array. Is it possible to realize it with a for loop, because i need the index later to calculate some features, for example the maximum and minimum and it's position or something like this? And this code should be synthesizable.

I hope somebody can help me. I am very grateful for this.

Altera_Forum · ‎07-18-2012

No, you cannot sum std_logic_vectors with standard VHDL. You can only perform arithmatic on unsigned or signed types. Std_logic_vectors are just an array of bits, so you have no idea if they are signed or unsigned or just a random bus.

So you need to convert them to signed or unsigned type first. You could easily write a function to sum the table. The question is, will vec_value always be a constant, or is it some kind of memory?

Altera_Forum · ‎07-18-2012

Thank's for the fast answer. My VHDL experience are not the best. This is a new section for me.

Yes, that's right. I have to convert std_logic_vector in unsigned / signed. Can i use integer too?

So, my idea for the implementation:


type table is Array (natural range <>) of std_logic_vector (7 downto 0);
constant vec_value: table := ("00000000","00000001","00000010","00000010","00000010","00000110","00010010");
begin
 signal tmp : unsigned := "00000000" ;
  
 process(CLK)
    begin
    if clk'event and clk = '1' then
       for i in 0 to 6 loop    
         tmp <= tmp + unsigned(vec_value(i));
        end loop;   
       SUM <= (tmp,8);
   end if;
end process;

Is it the right way? But do i need a clk?

--- Quote Start ---

The question is, will vec_value always be a constant, or is it some kind of memory?

--- Quote End ---

For the first time to lean about arithmetic operations i use constant's but later it will be elements of memory which are frequently change

Thank's a lot

regards

phot

Altera_Forum · ‎07-18-2012

Hi phot,

When writing VHDL, you need to think about what logic will be synthesized, and what logic you're just using to make the code more readable.

In some cases, it makes the code easier to read and maintain by using tables and constants containing integers or real values. This works well, if those tables and constants are only used to initialize synthesizeable logic, eg., to initialize std_logic_vector signals or variables.

For example, look in the following example code for a linear feedback shift register. The code essentially uses the VHDL compiler to perform matrix operations, the results of which are then used to define hardware:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/lfsr_tutorial.pdf)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial_src.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/lfsr_tutorial_src.zip)

The adder_tree.vhd component in that source is what you would need to use if you were adding values together in a parallel operation.

If you were adding values from RAM, then you would only need one adder, and a clock per RAM location to read the data and then sum it. Keep in mind that your sum will have more bits than the input, so you need to make your adder as wide as needed to store the largest sum, eg., the sum of 100 8-bit values is ceil(log2(100)) = 7-bits wider (eg., 100 x FFh = 639Ch).

Cheers,

Dave

Altera_Forum · ‎07-26-2012

Thank's a lot.

My FPGA is a Spartan 3AN XC3S1400AN which includes a Block RAM. How can i use it? Do i have to create in the Xilinx Core Generator a Block Memory Generator? Or do i need only a Block RAM Controller, because the Block Ram already exists?

best regards