Hi,I have the De1-SoC board. I wanted to implement an adder on fpga. The data are on the DDR3 of the HPS. I get access to them with a MSGDMA, what is controlled by the HPS. That works fine. The addition component gets it's values from MSGDMA over Avalon Streaming interface (sink and source). I can start the transaction and I get values back but here is the problem: I just add +1 to the input, but the output is +2 higher Example: 0+1 = 2 ??? is this possible? 4+1 = 6 ??? Where is the mistake? Can anyone help me? Thanks, Jules
If that's all your code, the mistake is to connect to the data line of the streaming interface without providing any handshake.
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity Addition is generic ( Number_of_Taps : integer := 2); PORT ( clk : in std_logic; reset : in std_logic; inDATA : in std_logic_vector (15 downto 0); outDATA : out std_logic_vector (15 downto 0) ); end Addition architecture rtl of Addition is begin outDATA <= std_logic_vector(signed(inDATA) + 1); end architecture;
Thank's for your answer.I have a Top vhdl with the avalon streaming interface. I use the following signals: valid, ready, data Now I found a way. I changed the Memory from the HPS DDR3 to a on chip memory. One memory is for the input, another for the outputs. Now there are the right values. Is there somebody who can explain me why i have wrong values with the HPS DDR3 memory? I am accessing it with the fpga to hps bridge. Linux has a limited memory. So I have no problem with the access.