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Hello,
Is there any way to dynamically force a pair of Agilex 5 (E-series) LVDS output pins to electrical idle/tri-state/floating (i.e. no differential voltage)? AN-635 describes a forceelecidle port option in the PHY for older devices, but nothing for Agilex 5 regarding either OOB signalling or electrical idle. I believe I can manually instantiate a differential I/O buffer with an output enable, but do I lose access to that enable if I am using the PHY IP in PCS-PMA direct mode?
This is for the purposes of a SATA host controller. The OOB signaling requires that the TX pin pair is held at 0 differential voltage between bursts.
Thank you
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Hi,
related to SATA, I read in most recent GTS Transceiver User Guide that PMA direct mode basically supports SATA protocol (paragraph 2.1 Building Blocks, Table 2) but not yet in latest Quartus version 25.1. "SATA mode is not supported in the current release of the Quartus® Prime Pro Edition software."
SATA support is also claimed in Architecture Brief Agilex™ 5 FPGAs: High-Speed Serial Interface (HSSI) Hard IP
GTS PHY has dedicated high speed differential I/O, no way to "instantiate" other I/O hardware.
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Hello,
Any updates on this issue? Does the answer provide helps you move forward? Or do you need more support on this?
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I will check this first and provide you with the answer as soon as possible.
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I checked with the internal team and been informed that we support SATA at 1.5G, 3G, 6G, but there is no hard IP. Let me know if you need more details.
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Hi,
thanks for checking SATA state. Questioned SATA Hard IP is probably a misunderstanding of quoted "High-Speed Serial Interface (HSSI)
Hard IP" architecture brief.
Open point is, when will SATA support be available at all. According to most recent Quartus 25.1 doc, it's not yet supported.
Regards
Frank
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Hello Frank,
I was informed that the User Guide for SATA for Agilex 5 is still in progress, and the Quartus release is tentatively planned to be around 25.1.1, subject to change.
Regards,
Aqid

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