Agilex 5 LVDS Serdes (Serdes factor 7 and 504Mbit/s valid?)

[TK99]

Hello,

I used  A10 and C10GX devices to implement a LVDS Serdes with 504MBit/s and a 1:7 ratio.
This is common interface towards LCD Panels (HD).

We are looking forward to use an Agilex 5 device for a new project but I can't find a solution to implement such an interfcae again. 

Agilex 5

- serdes factor of 1,2 (DDR), 4 or 8 is only valid

- the minimum rate starts at 600MBit/s

-the DDR performance is <= 500MBit/s 

What could I do to implement again such an interface?

best regards

 Tim

[FvM]

Hi,
if it's only LVDS TX (no CDR involved), SERDES can be easily implemented in FPGA fabric, Agilex 5 is fast enough, maximum core clock is 780 MHz for lowest speed grade. There might be other options, but your spec isn't completely clear for me.

[TK99]

Hi, 

Thank you for your reply!

I need an 504MBit/s LVDS output (4 lanes and one for clock 504MBit/7). 

For Arria10, Cyclone 10 GX and Agilex 7 were are LVDS Serdes Specs available to support this feature with a Serdes factor of 7 (internal clockrate 504/7) and a wide range regarding speed.

Right, the internal core frequency can be quite high for the A5.

But, The AC timing spec for Agilex5 has only Serdes factor of 4 or 8 and starting from 600Mbit/s (external).   

The Spec for the DDR (Serdes Factor 2) Performance is given by 500Mbit (not 504)

The Agilex 5 LVDS Serdes Datasheet looks different to the Arria10, Agilex 7.

[FvM]

Hi,
you won't necessarily use DDR register for the SERDES design. I presume that a SDR fast clock of 504 MHz and slow clock of 72 MHz will be PLL generated and SERDES implemented in registers.

[TK99]

Hi, 
an SDR (I/O) fast clock of 504MHz is not covered by the Data Sheet. 

I used a small demo implementation to figure is 504MBit feasible via I/O (without dedicated SERDES) and I have the strong feeling that the STA is doing a very pessimistic timing analysis. 

Both paths (Arrival and required) have the same clock source (outclk(0)  of the PLL) and in my opinion up to this point it is the 'same internal wire'  due we are talking about physical clock networks inside the FPGA.
Why is the timing estimation for both path up to Line 16 not the same?
Why is there a WC analysis beginning at the Input ref clock of the PLL?
In earlier days we had somethng like 'clock-path-pessimism-removal'. 

Any Explanation?

[FvM]

Hi,
Quartus doesn't complain when implementing the design with 504 MHz SDR SERDES, I believe it will work.

[TK99]

Hi,
due to the pessimistic STA -as given in the screenshot with the high amount of skew for the logical and physical clock netork,

I was not able to get a valid Timing report.

best regards

 Tim

[WZ2]

Hi there,

Yes, the Agilex 5's SERDES does not support rates below 600M when the factory is set to 4. So, 504 is not recognized as an acceptable parameter. Are you expecting to perform data stitching in this scenario?

​

Best regards，

WZ

[FvM]

Hi,
despite of beeing able to compile 504 MBPS SERDES in FPGA fabric with SDR clock, I basically agree that Agilex 5 SERDES features are diasppointing, even compared to low cost FPGA series like Cyclone 10 GX. The lack of standard SERDES widths, e.g. 10 commonly used for 8b/10b encoded data makes it unsuitable for many standard communication applications. 

Regards

Frank