Agilex 5 - configure FPGA from running linux via dt-overlay

[MM-ATH]

Hello,

I am using HPS-first configuration scheme and I can fit FPGA from u-boot(first time it is successfull). Now I want to refit FPGA from running linux system. I am trying to follow this manual

https://device.report/m/dfbc733be8e55f3eeb1bd826b10d227bc67cef0500f56fd4ceedb63459e4e408.pdf

section 6.2. Configuring the FPGA Fabric from Linux, but I am getting error:

# echo fpga_core.dtb > /sys/kernel/config/device-tree/overlays/0/path
sh: write error: Invalid argument

this is my overlay dts file

/dts-v1/;
/plugin/;
/ {
  fragment@0 {
    target-path = "/soc/base_fpga_region";
    #address-cells = <1>;
    #size-cells = <1>;
    __overlay__ {
      #address-cells = <1>;
      #size-cells = <1>;
/*      ranges = <0x00000000 0xF9000000 0x00200000>;*/
      firmware-name = "fpga_core.rbf";
      config-complete-timeout-us = <10000000>;

/*      sysid@0 {
        compatible = "altr,sysid-20.1", "altr,sysid-1.0";
        reg = <0x00000000 0x00000008>;
        id = <0x12345678>;
        timestamp = <0>;
      };*/
    };
  };
};

I have tried dts also with commented lines, also without success.

dmesg relevant lines:

STARTUP:
...
[    0.036001] FPGA manager framework
...
[    1.591366] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[    1.598563] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
[    1.606865] Stratix10 SoC FPGA manager soc@0:firmware:svc:fpga-mgr: couldn't get service channel (fpga)
...
[    1.706286] stratix10-svc soc@0:firmware:svc: Adding to iommu group 3
[    1.717674] Intel Service Layer Driver Initialized
...
[    1.768068] fpga_manager fpga0: Stratix10 SOC FPGA Manager registered
[    1.795620] of-fpga-region soc@0:base_fpga_region: FPGA Region probed
...

Dduring DT overlay apply:
[  575.816996] OF: overlay: find target, node: /fragment@0, path '/soc/base_fpga_region' not found
[  575.825722] OF: overlay: init_overlay_changeset() failed, ret = -22
[  575.831968] create_overlay: Failed to create overlay (err=-22)

in ...intel/socfpga_agilex5.dtsi there is section:

...
  soc: soc@0 {
    compatible = "simple-bus";
    ranges = <0 0 0 0xffffffff>;
    #address-cells = <1>;
    #size-cells = <1>;
    device_type = "soc";
    interrupt-parent = <&intc>;

    base_fpga_region {
      #address-cells = <0x2>;
      #size-cells = <0x2>;
      compatible = "fpga-region";
      fpga-mgr = <&fpga_mgr>;
    };
...

according this page

https://www.rocketboards.org/foswiki/Documentation/IntelFPGAHPSEmbeddedSoftwareRelease

there was problem

FPGA configuration with overlays fails after seeing the following message during Linux boot up: "Stratix10 SoC FPGA manager soc:firmware:svc:fpga-mgr: couldn't get service channel (fpga)"

, but it should be fixed in 24.2 PRO version (I am using 24.3.1 PRO version)

Could you help me wth this problem, please? Is problem the target_path variable?

[MM-ATH]

It seems, that target_path variable should be 

target-path = "/soc@0/base_fpga_region";

but after "echo fpga_core.dtb > /sys/kernel/config/device-tree/overlays/0/path" system hangs. This is output on serial line:

echo fpga_core.dtb > /sys/kernel/config/device-tree/overlays/0/path
[ 39.285147] fpga_manager fpga0: writing fpga_core.rbf to Stratix10 SOC FPGA Manager
PANIC at PC : 0x000000008000b420

Maybe it is necessary to manually disable bridges or something else that is beyond my knowledge...

Any advice is welcome.

[MM-ATH · Accepted solution]

Hi all,

finally I solved issues with help from Arrow (thank you Tomasz). The necessary things were:

1) to modify u-boot script to exclude any accesses to fabric peripherals (eg USB reset PIO)

echo "Trying to boot Linux from device ${target}";

if test ${target} = "mmc0"; then

  mw.l 10d13224 14;
  mw.l 10d13228 14;
  mw.l 10d1323c 14;
  mw.l 10d13234 14;
  mw.l 10d13248 14;
  mw.l 10d1324C 14;
  mw.l 0x10D11028 0x01027fb0 1;
  mw.l 0x10c03304 0x410 1;
  mw.l 0x10c03300 0x00000410;
  mw.l 0x10c03300 0x00000000;
  mw.l 0x10c03300 0x00000410;

else
    echo "mmc0 not found!"
fi

fatload mmc 0:1 ${loadaddr} ${bootfile};
setenv bootargs "bootargs console=ttyS0,115200 root=${mmcroot} rw rootwait";
bootm ${loadaddr};

if test ${target} = "qspi"; then
  qspi_clock=0x17d78400;
  if ubi part root; then
    ubi detach;
    mtdparts;
    ubi part root;
    ubi readvol ${loadaddr} kernel;
    ubi detach;
    setenv bootargs "earlycon panic=-1 ubi.mtd=1 root=ubi0:rootfs rootfstype=ubifs rw rootwait";
    bootm ${loadaddr};
  fi
  ubi detach;
  sf probe;
  sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize};
  setenv bootargs "earlycon root=/dev/mtdblock1 rw rootfstype=jffs2 rootwait";
  bootm ${loadaddr};
fi

if test ${target} = "nand"; then
  ubi part root;
  ubi readvol ${loadaddr} kernel;
  setenv bootargs "earlycon panic=-1 root=${nandroot} rw rootwait rootfstype=ubifs ubi.mtd=1";
  bootm ${loadaddr};
fi

2.)  To modify  and rebuild the devicetree (socfpga_agilex5_axe5_eagle.dts). Remove any references to fabric peripherals - so LEDs sections, whole soc@0 section and &usb31 section.

overlay.dts was also simplified

// SPDX-License-Identifier:     GPL-2.0
/*
 * Copyright (C) 2024, Arrow Electronics, Incorporated.
 */

/dts-v1/;
/plugin/;

/ {

  fragment@0 {
    target-path = "/soc@0/base_fpga_region";
    __overlay__ {
      firmware-name = "axe5_eagle_top.hps.core.rbf";
      config-complete-timeout-us = <30000000>;
    };
  };
};

and now fpga_core.rbf can be (for first time) succesfully load also from linux system.