Agilex DDR4 Interface Debug

[emrahener]

EMIF Toolkit does not support Agilex Family FPGAs but EMIF IP user guide still address this toolkit for JTAG debugging.

http://www.audentia-gestion.fr/INTEL/PDF/ug-ag-emi.pdf Page :105. 

Is there a suggested methodology and/or  tool for debugging DDR4 interfaces through JTAG? 

Can we debug HPS DDR4 using the same methodology?

Kind Regards,

Emrah ENER

[AdzimZM_Intel]

Hi Emrah,

"EMIF Toolkit does not support Agilex Family FPGAs but EMIF IP user guide still address this toolkit for JTAG debugging."

Which EMIF Toolkit that you mean here?

"Is there a suggested methodology and/or tool for debugging DDR4 interfaces through JTAG? "

You can debug the EMIF interface with EMIF Debug Toolkit or On Chip Debug Port. The details can be referred to links below:

• https://www.intel.com/content/www/us/en/docs/programmable/683216/22-4-2-6-1/debugging-with-the-external-memory-interface.html
• https://www.intel.com/content/www/us/en/docs/programmable/683216/22-4-2-6-1/emif-on-chip-debug-port.html

"Can we debug HPS DDR4 using the same methodology?"

To debug the HPS EMIF, we will use Fabric EMIF IP with HPS EMIF pin placement. The HPS EMIF is not supported by the debugging tools.

Regards,

Adzim

[emrahener]

The EMIF Toolkit  I am mentioning is 

Tools / System Debugging Tools / External Memory Interface Tool Kit . I also attached the  related screen shots.

Where can I open EMIF Debug Toolkit  if it is not the one I mentioned.

Kind Regards,

Emrah ENER

[AdzimZM_Intel]

Hi Emrah,

Can you confirm that the EMIF Debug Toolkit has been enabled in the design?

Regards,

Adzim

[sstrell]

For Agilex, the EMIF debug toolkit is accessed through System Console, not what you are selecting in the screenshot.  Open System Console first and you'll then find the option for the toolkit.

[AdzimZM_Intel]

Hi Emrah,

Are you still facing the issue at the moment? Any update in this thread?

Regards,

Adzim

[emrahener]

I got access to EMIF toolkit through system console when I downloaded the Example Design. 

Thanks for your support.

[emrahener]

Hi,

Can you please be more specific with `EMIF Debug Toolkit has been enabled`. ?

External Memory Interfaces Intel Agilex IP has a parameter in Diagnostics Tab. 

Disabled : Certainly we dont want this .

Export : EMIF debug interface IP core is not among available IP list in IP Catalog.

I selected Add EMIF Debug Interface and Rerunned the whole flow starting from Generate HDL. When I downloaded the .sof file I could not see any selection in the system console system (Debugger Tools /System Console). 

Since the related parameter is under the title Example Design (Diagnostics Tab not Example Design Tab) I generated the example design and will try downloading the resultant sof file .

Specifies the connectivity of an Avalon slave interface for use by the Quartus Prime EMIF Debug Toolkit or user core logic.

If you set this parameter to "Disabled", no debug features are enabled. If you set this parameter to "Export", an Avalon slave interface named "cal_debug" is exported from the IP. To use this interface with the EMIF Debug Toolkit, you must instantiate and connect an EMIF debug interface IP core to it, or connect it to the cal_debug_out interface of another EMIF core. If you select "Add EMIF Debug Interface", an EMIF debug interface component containing a JTAG Avalon Master is connected to the debug port, allowing the core to be accessed by the EMIF Debug Toolkit.

[sstrell]

See this training for details on this:

https://cdrdv2.intel.com/v1/dl/getContent/652834

[AdzimZM_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.