All 1.2V drivers in the Agilex IBIS model with slew rates of S0 or S1 show serious stair stepping. This can be seen simply by viewing the Rising/Falling Waveforms with an IBIS viewer or in a simple simulation with a driver and termination. Only slew rate S2 (fast) has a reasonable rise/fall waveform.
Driver models showing this include LVCMOS, HSUL, HSTL, and SSTL - pretty much anything except LVDS.
Is it possible the IBIS model (rev 1.2, July 2020) is incorrect?
Would you able to attach more details on your finding? Also, do you have comparison of other devices if they also carry such behaviour or it is just on Agilex model?
We assume you are getting the model from
Thanks for your question. Seeing the waveform certainly is easier than trying to describe it. I'm attaching a simple summary of what the IBIS model for the Agilex SSTL12 contains for its 'Rising Waveform' for the three slew rate choices. The IBIS file is the latest one posted on Intel's website (even though it is from last July).
In my many years of using IBIS models to simulate interfaces, mostly DDRx, I have never seen this behavior in a model and so doubt it represents the actual silicon. I mention this because the default setting in the EMIF tool for DDR4 address/control is 'medium slew rate', or S1. We have working designs running on the Agilex Evaluation Board using those default settings, driving an RDIMM at, I believe, 3200MTPS without any issues. The IBIS sstl12 driver, using S1, could never form an eye at those rates (or any useful rate for that matter).
The IBIS model for Stratix10 devices contains drivers for various SSTL levels which include slow and fast (0 and 1) slew rate settings - but not for the 1.2V SSTL12. The S0 drivers for SSTL125, SSTL135, etc look fine, and a bit slower in slew than the S1 as expected.
Since even the Agilex LVCMOS 1.2V IBIS driver shows the strange stair step, we plan to drive a test connector on the Agilex Eval Board to verify that the edge doesn't actually do that. I will post our results.
Thanks for the updates and yes the wave doesn't look good. Once you verify on the actual board, I can help bring it to Engineering as I couldn't found similar issue in the database at this moment.
We were able to confirm that the silicon creates the same slew rate and waveform as the IBIS model. I would encourage anyone designing memory channels with the Agilex FPGA family to simulate the channel (Intel recommends this also). You basically have two choices for slew rate (the slow slew rate is over 1ns so is completely useless for DDRx channels regardless of operating speed). The medium slew rate has the stair step edges so will create a very interesting eye. While it may have a clear 'center' that might actually pass setup/hold with a bit of margin, that center will be far smaller than if the edges were not stepped. Using the fast slew rate you have a different problem if you're driving anything but an RDIMM with one load. The edge rate will cause reflections off of the DRAM package internal traces which cause resonances along the channel. This collapses the eye at some of the DRAMs regardless of how well you've crafted your PCB and tuned your termination. It's hard to know which is worse, a collapsed eye due to slew rate and stair stepping or a collapsed eye due to reflections. For our discrete channels we will start with the medium slew rate and see how much margin we get. The calibration should help in centering the clock in whatever opening can be found at each DRAM. But if you're just driving RDIMMs, you're all good with the fastest slew rate driver.
I have an update - I am hearing from Intel that there will be an updated IBIS model that includes compensation for the S1 (medium) slew rate drivers. This compensation controls how long the step lasts essentially changing the effective slew rate. It appears this could shorten the rise time of the S1 slew rate to around 200ps which is, based on my simulations, optimal for address/control signals running at 1.6GHz. This is very good news! I assume the EMIF tool will also be updated to allow selection of a compensation value (I need to check to see if it's already there but just not in the IBIS model, which would be strange). In the end the eyes at each DRAM should look pretty darn good, which is a huge relief. Watch the website for the updated IBIS model (no ETA).
I am also seeing the strange stair-stepping behaviour when using the 1.2V IO IBIS models, even in the updated December 2021 models. Is this the actual way an Agilex device drives a slow or medium signal? If so I can't think of a situation where these would ever be usable. Is there a way to compensate for the stair-stepping in the model?