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Agilex5 IOPLL simulation

Frank741
Beginner
527 Views

 

Hi,

Why my IOPLL simulation output xx?The input clock and reset is right. 

 

Frank741_1-1724114017730.png

Quatus24.2,Agilex5 

 

Thanks for help

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AqidAyman_Intel
Employee
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We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum cases, along with others, did not get through as intended. As a result, we have a backlog of cases that we are currently working through one by one.

Please be assured that we are doing everything we can to resolve this issue as quickly as possible. However, this process will take some time, and we kindly ask for your patience and understanding during this period. The cases will be attended by AE shortly.

We appreciate your patience and understanding, and we are committed to providing you with the best support possible.

Thank you for your understanding.


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AqidAyman_Intel
Employee
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Hi Frank,


You can increase the simulation timeframe to see if the outclock signal starts to toggle.


Regards,

Aqid


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AqidAyman_Intel
Employee
291 Views

Wish to follow up with you, do you need further support on this? Do you have any more questions?


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