Altera MAX 10 CPLD development

[Matthew99]

Hi all,

I use Altera MAX 10 CPLD at BMC system,
is there any documents talking MAX 10 development, programming
What kind of software I need to install?
where to download MAX 10 datasheet?

Thanks

[sstrell]

Right from the Intel web site: https://www.intel.com/content/www/us/en/products/details/fpga/max/10.html

Quartus download center: https://www.intel.com/content/www/us/en/products/details/fpga/development-tools/quartus-prime/resource.html

[Matthew99]

Hi @sstrell 

Thanks for your kind reply.

the simple diagram of main board is as below:

the CPLD fw will be pushed to BMC via redfish, then BMC need to update CPLD fw.

this is different from using JAG pin to program CPLD fw.

for this kind of scenario, how to program CPLD fw by BMC linux OS? is there any available program from Quartus Prime software I can use?

Any suggestions will be appreciated.

Thanks

[WZ2]

Hi there,

As I understand it, you need to update the content of the CFM in the MAX10 via the FPGA's I2C interface. This functionality has a reference design. You can refer to the demo design in this link. The demo design transfers data to the MAX10 via the I2C interface, where the Nios processor inside the MAX10 writes the data into the CFM.

https://www.intel.com/content/www/us/en/design-example/714747/intel-max-10-fpga-i2c-remote-system-update-design-example.html

Best regards,

WZ