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Altera Max II and correct software to use to figure out checksum code

jctis
Beginner
108 Views

hi, i am new to the intel FPGA world and my background is in micro-controllers, so i apologize if this is the wrong section to start this in. figured i would ask before spending weeks chasing something that wont work. and figured this was a good project to learn a new discipline.

my situation is that i have a board(s) that has an Altera Max II EPM1270F25615N that interfaces to a flash memory (intel 28F800). the problem with these boards is they fail a checksum when booting and halt. i suspect the corrupted flash was a design flaw by the board maker and not with these chips, but the end result is the same, wont boot. i have narrowed it down to the code stored in the Flash as being the problem (possible the altera), and i have been able to read the data in the flash, but i cant just copy over the working code read to a new chip as there is history data that needs to be preserved (power cycle counts, error history, etc) and more importantly, it appears that the altera and flash code are somehow binded together. no idea yet why the two would be coupled together in code. i have to move both the altera and the flash from a good board to a bad board to get it to work.

i have attempted to contact the OEM, which due to covid has gone out of business, so that avenue is a dead end. so my questions are:

1) will the Quartus software be able to read the extracted bin file (or HEX) and display readable code/program?

2) do i need some form of de-compiler first before the Quartus software will read/display a useful program

3) would the bin file need to be converted or aligned MSB/LSB first?

 

any advice on the approach and software to use is greatly appreciated.

 

j

 

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1 Reply
ak6dn
Valued Contributor III
96 Views

1) No, Quartus can't do that.

2) No such compiled binary to source code disassemblers exist.

3) Really irrelevant.

 

Without a board schematic and the original source code for the Altera part you are really embarking upon a nigh impossible task.

For a first FPGA project I would look elsewhere.

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