- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi everyone,
I want to use the I2C Controller on HPS to control a slave connected to the FPGA. So for my understanding I can use I2C pin multiplexing with option "FPGA" while configuring the HPS System to make the I2C Controller available to the FPGA. After this configuration, the i2c0_clk clock frequency can be modified. But what is this clock for? Or in general what is "Peripheral FPGA Clocks" for? Also I expected only two pins that could be connected to the FPGA, namely SCL and SDA but there are 4 Pins in total that are generated from Qsys: hps_0_i2c0_out_data : out std_logic; -- out_data (is this sda_out?) hps_0_i2c0_sda : in std_logic := 'X'; -- sda hps_0_i2c0_clk_clk : out std_logic; -- clk (peripheral fpga clock??) hps_0_i2c0_scl_in_clk : in std_logic := 'X'; -- clk I attached a screenshot for the configuration. https://www.alteraforum.com/forum/attachment.php?attachmentid=7499 I really appreciate your help! HanelLink Copied
2 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Basically you have to create the tristate logic using FPGA resources. I2C assumes that there are pullups on the bus lines so you just have to control when the pin is an input or driving out ground (driving out high is taken care of by the pullup on the bus).
Here is the mapping: _sda --> this is the input data from the SDA pin _out_data --> this is the output enable that you should use to drive a logic '0' out of the SDA pin _scl_in_clk --> this is the input clock from the SCL pin _clk_clk --> this is the output enable that you should use to drive the SCL pin So you would need something like this (Verilog.... my VHDL is too rusty): assign sda_pin = (out_data == 1)? 1'b0 : 1'bZ; // so when the output enable is high drive out a zero, other wise go Hi-Z assign hps_0_i2c0_sda = sda_pin; Those peripheral clock settings are used to provide the tools information about the clock rates of the data moving back and forth between the FPGA fabric (and eventually I/O) and the HPS so that the on-chip constraints can be set accordingly. Since cores like the I2C are not parameterizable IP (hard silicon) this is the only way for the user to tell the tools what frequency they plan to operate them at.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Oh and keep an eye out for a new SoC forum I'll be creating soon, I don't know where I'm putting it yet in the Altera forum but it should make asking questions like these a little easier.
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page