Altera Stratix V FPGA (P/N: 5SGSMD8N2F45C2L)

[user153746]

This part is supplied via two separate power rails (1.8V and 3.3V). The 1.8V rail supplies the VCCINT and VCCI02 pins, and the 3.3V supplies the the VCCI01 pins. The 1.8V rail comes up to voltage in 1ms while the 3.3V comes up to voltage in 20-40ms. Will this delay between the two rails coming up to power adversely affect the FPGA?

[AqidAyman_Intel]

Hi,

Thank you for reaching out to Intel FPGA Community.

Before I answered your question, can I confirm on the symbol, is it VCC you refer as VCCINT? This is because when I checked the datasheet, the absolute maximum value for VCC of Stratix V Device is 1.35V. Based on your question, you mentioned you supply it with 1.8V.

Can you confirm this first?

[user153746]

Hello,

Apologies for the confusion. The VCC pins are receiving 0.85V, and the 1.8V rail is feeding VCCIO8A through VCCIO8B. 

Thanks.

[AqidAyman_Intel]

Hi,

The power-on reset (POR) circuitry keeps the FPGA in the reset state until the power supply outputs are in the recommended operating range.

A POR event occurs from when you power up the FPGA until the power supplies reach the recommended operating range within the maximum power supply ramp time, tRAMP . If tRAMP is not met, the device I/O pins and programming registers remain tri-stated, during which device configuration could fail.

The tRAMP for Stratix V is between 200 microseconds to 100 ms for Standard POR while 200 microseconds to 4 ms for Fast POR.

[AqidAyman_Intel]

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