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Hi all;
I have previous problem that still cannot solve. I have try to use the new version of quartus2 but the internal error still occur. I also have try to delete the db and db_increment directory but still not work. The compilation is work for the first time, before I turn on the Generate Value Change Dump File Script option (Assignments>Settings). Below is my code and the internal error: ---------------------------------------------------------------------------------------- library ieee; library ieee_proposed; use ieee_proposed.fixed_pkg.all; package my_data_types is type sfixed_array_t is array (0 to 3) of sfixed (9 downto -8); end my_data_types; library ieee; library ieee_proposed; use ieee_proposed.fixed_pkg.all; use work.my_data_types.all; entity reg_one is port (clk: in bit; Ra: in sfixed_array_t; out_Ra: out sfixed_array_t); end reg_one; architecture reg_one of reg_one is begin process(clk) begin if (clk'event and clk='1') then for i in 0 to 3 loop out_Ra(i) <= Ra(i) after 10ns; end loop; end if; end process; end reg_one; ---------------------------------------------------------------------------------- Internal Error: Sub-system: WSC, File: /quartus/neto/wsc/wsc_port.cpp, Line: 514 m_port_info.num_of_dimensions() == 1 Stack Trace: 0x251D8 : WSC_PORT::bus_member_index + 0x88 (NETO_WSC) End-trace Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition ------------------------------------------------------------------------------------ Can anyone helps me please..really need helps. ThanksLink Copied
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try quartus 11.
Otherwise you will need to raise a request with altera MySupport. Only they can diagnose internal errors. Secondly - why are you using "after" in the code? you realise it is ignored for synthesis? but why would you want it in a clocked process anyway?- Mark as New
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Yes, I already send a request to the altera MySupport.
I want to generate the output after 10ns..thanks for reply- Mark as New
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Delays like that are not possible on real hardware. You will have to run a 100Mhz clock and delay your data by 1 clock to acheive a 10ns delay.
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How can I make the delays 10ns on the real hardware? Some books write like out <= in after 10ns for have a delay..
thanks for reply- Mark as New
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you can only do it with a clock.
The code you are seeing is for simulation purposes only.- Mark as New
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Thanks Tricky..:)
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