10-25-2017 10:51 AM
Hi Venkat,I believed you are referring to Avalon Memory Map interface. Avalon interface is generally a bus interface used to connect multiple different design IP block together. You can find out more about Avalon Interface spec in https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pd... Thanks. Regards, spdl2001 (This message was posted on behalf of Intel Corporation)
10-25-2017 12:53 PM
The interconnect is generated by Qsys based on component parameter settings and connections between component interfaces. A better resource for learning about the interconnect would be the Quartus Prime Handbook.