This file would have information under [Define Package Model] in an IBIS file and be specific for each FPGA package. It correlates to the netlengths available on the website used for DDR/high speed length matching and analysis. Thanks!
Here is the IBIS package available for all FPGA device, including Arria 10.
IBIS model is depend on which IO standard and termination setting that you set in the Quartus design.
As I know, that is the only IBIS model that available. It allow you to run the IBIS simulation based on specific IO. If you want o include the package delay, you can get the pin net length following the instruction as stated in this link: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...
Hope this helps
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