Community
cancel
Showing results for 
Search instead for 
Did you mean: 
RGard2
Novice
496 Views

Are there known issues with accessing external DDR from the FPGA fabric on an Arria 10 SoC when using the Linux 4 kernel?

Note that we had no issues when using the Linux 3 kernel, but we are having issues now that we have moved to the Linux 4.20 release. Registers in the FPGA fabric can be written and read back successfully, so no issues in general with access between the HPS and the FPGA fabric. It seems to be related only to the interface between the FPGA and external DDR that it uses.

 

Thanks in advance!

0 Kudos
4 Replies
71 Views

Hi,

 

Can you elaborate the specific issue? Do you mean that for both Linux 3 and 4.20, the registers in the FPGA fabric can be written and read back? or just for Linux 3?

 

You can try this External Memory Interfaces Intel Arria 10 FPGA IP Design Example User Guide, this might help:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20118.pdf

 

Regards.

 

RGard2
Novice
71 Views

Hi,

 

Thanks for the reply.

 

We are able to read/write registers in the FPGA when using both Linux 3 and Linux 4.20. External DDR is connected to the FPGA for expanded storage. There are registers in the FPGA that reflect the status of the DDR calibration during initialization. On startup, we write/read registers in the FPGA (for configuration) and we read the aforementioned FPGA registers to check the status of the DDR calibration. We read back a successful status when using Linux 3 but a bad status (calibration complete is never indicated) when using Linux 4.20. Just want to re-iterate that we know we are reading/writing registers in the FPGA correctly in Linux 4.20, so it seems to be an issue specific to the DDR calibration, interface, operation, etc.

 

Thanks for the user guide, I'll take a look. If you have any other feedback, it would be greatly appreciated.

 

Thanks again and best regards.

 

 

71 Views

Hi,

 

What is the specifications of the DDR that you are using on the FPGA fabric?

RGard2
Novice
71 Views

Issue resolved. There was a floating GPIO that fed the resets of the DDRs.

 

el.ign - Thanks for your suggestions and assistance.

Reply