Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20693 Discussions

Are there more than just one SERDES IP allowed one one Arria10 GX IO Bank?

Jens
Novice
572 Views

I have to split 4 physical LVDS groups (32 channels each) over 6 Arria10 GX IO Banks (max. 24 channels). Each group has its own reference clock. The question is can I have 2 SERDES with DPA in one IO Bank?

 

Jens

0 Kudos
1 Reply
Rahul_S_Intel1
Employee
296 Views

Hi Jeans,

Have to tried to compile the design the got any fitter Error based on the above assumption. In my point of view you can do it

0 Kudos
Reply