Arria 10 Clock Input - Differential POD 1.2V I/O Standard

[Altera_Forum]

We are currently using an Arria 10 SX 270 F34 device for a project, and due to a limited number of I/O banks I want to use a spare differential pair on one of the DDR4 I/O banks as a clock input to an IOPLL. 

 However, as the DDR bank is stuck at 1.2V, I have been trying to find a way to connect an LVDS signal to a 1.2V I/O bank. We are using a dev-kit, so it's not possible to add an external termination resistor close to the FPGA I/O pins, limiting the options to the four I/O standards that the A10 supports internal termination four - HSTL12, SSTL12, HSUL12 and Differential POD12.  I've worked out that using an LVDS to CML converter, it should be possible to use the differential POD12 I/O standard with 48Ohm Rt and a VCCIO of 1.2V. As such, I've made the following IO assignments:  set_location_assignment PIN_AD10 -to refclk_in set_location_assignment PIN_AD11 -to "refclk_in(n)" set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.2-V POD" -to refclk_in set_instance_assignment -name INPUT_TERMINATION "PARALLEL 48 OHM WITH CALIBRATION" -to refclk_in  However, when I try to compile the design in Quartus 17.1, I get the following error:  Error (18314): I/O pin refclk_in is driving a ref clock and has a pseudo-differential I/O standard. Try setting the I/O standard to a true differential I/O Standard Error (18314): I/O pin refclk_in(n) is driving a ref clock and has a pseudo-differential I/O standard. Try setting the I/O standard to a true differential I/O Standard  I'm now confused as to what Quartus is complaining about? I am using a true differential I/O standard according to the datasheet:    --- Quote Start ---  5.5.5.2.1. Differential HSTL, SSTL, HSUL, and POD Termination 

• Differential HSTL, SSTL, HSUL, and POD inputs use LVDS differential input buffers. However, RD support is only available if the I/O standard is LVDS. 
• Differential HSTL, SSTL, HSUL, and POD outputs are not true differential outputs. These I/O standards use two single-ended outputs with the second output programmed as inverted. 

   --- Quote End ---    I'm using them as differential inputs, which apparently use LVDS differential input buffers. So surely they are true differential I/O?