Arria 10 DDR4 on Banks 3B and 3C?

[RobertoB]

Are Banks 3B and 3C available to be configured for use with DDR4 interface? 

The documentation below calls out the restrictions on Banks 2A, 2I, 2J, 2K, but I'm unsure what is applicable to 3B and 3C.

3.7.1. Restrictions on I/O Bank Usage for Intel® Arria® 10 EMIF IP...

Thank you for you help.

[sstrell · Accepted solution]

The restrictions you link to are only if you are using an EMIF with the HPS in an SoC variant of the device.

If you are not using an SoC or you want to implement memory interfaces not directly connected to the HPS, then 3B and 3C should be fine.

https://www.intel.com/content/www/us/en/docs/programmable/683106/21-1-19-2-0/i-o-column.html

[RobertoB]

Thank you for your reply!

My question is in reference to an A10 SX device -- so using an EMIF with the HPS of an SoC device. Combing through the restrictions document linked in the original post, I did find the following language:

Intel® Arria® 10 SX devices have 3 modular I/O banks (2K, 2J, and 2I) that connect the HPS to an SDRAM through a dedicated HPS EMIF. Each bank has 4 I/O lanes that correspond as follows:

• Lane 3: IO[47:36]
• Lane 2: IO[35:24]
• Lane 1: IO[23:12]
• Lane 0: IO[11:0]

Based on this my understanding is that only 2K, 2J, and 2I are suitable to be configured for use with DDR4. Does that seem correct, or am I missing something?

Thanks!

[sstrell]

This is what you must use if you want the EMIF connected to and directly accessible by the HPS, so if that's what you want to do, then yes, you must use those banks.  Other I/O banks not mentioned in the page you linked to can be used for EMIFs but they connect to the FPGA fabric, requiring a longer latency to access from the HPS (you'd have to access via the H2F bridge instead of direct SDRAM access).